February 2005
ASM3P2508SP
rev 0.4
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Features
Dual PLL based Architecture
Operates with a 3.3V 0.3V supply.
Generates an EMI optimized Spread Spectrum
PCI Clock output
Generates a high accuracy non Spread T1 clock of
25ppm accuracy.
Generates a non spread system reference clock
Low power CMOS design.
Input frequency: 25 MHz.
Outputs:
Sys_ REF_CLK: 20 MHz
T1 Clock: 25 MHz (25 ppm)
PCI_CLK: 33.33MHz Spread Spectrum
Frequency deviation: -0.5% (Typ).
Available in 8L SOIC Package.
Product Description
The ASM3P2508SP is a versatile Dual PLL based Clock
Synthesizer and Frequency Generator optimised and
designed specifically for three clock frequencies. The
PCI_CLK output from ASM3P2508SP reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. ASM3P2508SP allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads & shielding that are
traditionally required to pass EMI regulations.
The ASM3P2508SP uses the most efficient and
optimized modulation profile approved by the FCC.
ASM3P2508SP modulates the output of a PLL in order to
"spread" the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in a significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal's bandwidth is called `spread
spectrum clock generation' (SSCG).
In addition to the SSCG output, ASM3P2508SP
generates two high accuracy clock signals -
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a
20MHz Sys_ REF_CLK.
Applications
The ASM3P2508SP is targeted towards Consumer,
Industrial, Data and Telecommunications applications.
Key Specifications
Description
Specification
Supply voltages
V
DD
= 3.3V 0.3V
Input Frequency
25 MHz
Cycle-to-Cycle Jitter
175 pS ( Max)
Output Duty Cycle
45/55%
Output Rise and Fall Time
1.1 nS (Max)
SSC Modulation Rate
30KHz (Typ)
SSC Frequency Deviation
-0.5% (Typ)
Block Diagram
V
SS
T1_CLK
Sys_REF_CLK
V
DD
Modulation
XIN/CLKIN
Input
Divider
Osc
PLL 1
Output
Divider
PLL 2
PCI_CLK
XOUT
Output
Divider
PWRDNB
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Clock Synthesizer and Frequency Generator with Peak EMI reduction
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Notice: The information in this document is subject to change without notice.
PWRDNB
XOUT
1
2
3
4
5
6
7
8
ASM3P2508SP
XIN/CLKIN
Sys_REF_CLK
PCI_CLK
V
SS
T1_CLK
V
DD
Pin Configuration
Pin Description
Pin#
Pin Name
Type
Description
1 XIN/CLKIN I
Crystal connection or external reference frequency input. This pin has dual functions.
It can be connected either to an external crystal or an external reference clock.
2
XOUT
O
Crystal connection. If using an external reference, this pin must be left unconnected.
3 V
DD
P
Power supply for the entire chip
4
Sys_REF_CLK
O
PLL 1 output System Reference Clock @ 20MHz
5 PWRDNB I
Power-down control pin. Pull low to enable power-down mode. Connect to V
DD
if not
used. Power -down Mode shuts off all the Outputs.
6
PCI_CLK
O
PLL 2 Spread spectrum clock output @ 33.33MHz
7 V
SS
P
Ground to entire chip. Connect to system ground
8
T1_CLK
O
Reference output T1 Clock @ 25MHz
Typical Modulation Profile
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
T
STG
Storage temperature
-65 to +125
C
T
A
Operating temperature
0 to 70
C
T
s
Max. Soldering Temperature (10 sec)
260
C
T
J
Junction
Temperature
150
C
T
DV
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
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Clock Synthesizer and Frequency Generator with Peak EMI reduction
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Notice: The information in this document is subject to change without notice.
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25C) unless otherwise stated)
Symbol
Parameter
Min
Typ
Max
Unit
V
IL
Input low voltage
V
SS
- 0.3
0.8
V
V
IH
Input high voltage
2.0
V
DD
+ 0.3
V
I
IL
Input low current
-35
A
I
IH
Input high current
35
A
I
XOL
XOUT output low current (@0.4V, V
DD
=3.3V)
3
mA
I
XOH
XOUT output high current (@2.5V, V
DD
=3.3V)
3
mA
V
OL
Output low voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
0.4
V
V
OH
Output high voltage (V
DD
= 3.3 V, I
OH
= 20 mA)
2.5
V
I
DD
Static supply current *
10
A
I
CC
Dynamic supply current
(3.3V, 33.33MHz, 25MHz , 20MHz and 15pF loading)
20 _ mA
V
DD
Operating
voltage
3.0 3.3 3.6 V
t
ON
Power-up time (first locked cycle after power up)**
5
mS
Z
OUT
Clock output impedance
50
* PWRDNB pin is pulled low
** V
DD
and XIN/CLKIN input are stable, PWRDNB pin is made high from low.
AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
XIN
Input frequency
25
MHz
PCI_CLK
33.33 MHz
T1_CLK 24.999375
25
25.000625
Sys_REF_CLK
Output frequency
20
MHz
Modulation Rate
30
KHz
PCI_CLK (SSCG)
Deviation
-0.5
%
t
LH
*
Output rise time (measured at 0.8V to 2.0V)
0.7
0.9
1.0
nS
t
HL
*
Output fall time (measured at 2.0V to 0.8V)
0.6
0.8
1.0
nS
t
JC
Jitter (cycle to cycle)
150
175
pS
t
D
Output duty cycle
45
50
55
%
* t
LH
and t
HL
are measured into a capacitive load of 15pF
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Clock Synthesizer and Frequency Generator with Peak EMI reduction
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Notice: The information in this document is subject to change without notice.
Typical Crystal Oscillator Circuit
Typical Crystal Specifications
Fundamental AT cut parallel resonant crystal
Nominal frequency
25 MHz
Frequency tolerance
25 ppm or better at 25C
Operating temperature range
-25C to +85C
Storage temperature
-40C to +85C
Load capacitance
18pF
Shunt capacitance
7pF maximum
ESR 25
R1 = 510
C1 = 27 pF
C2 = 27 pF
Crystal
February 2005
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Clock Synthesizer and Frequency Generator with Peak EMI reduction
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Notice: The information in this document is subject to change without notice.
Package Information
8-lead (150-mil) SOIC Package
D
E
H
D
A1
A2
A
L
C
B
e
Dimensions
Inches
Millimeters
Symbol
Min
Max
Min
Max
A1 0.004 0.010 0.10
0.25
A 0.053
0.069 1.35 1.75
A2 0.049 0.059 1.25
1.50
B 0.012
0.020 0.31 0.51
C 0.007
0.010 0.18 0.25
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L 0.016
0.050 0.41 1.27
0 8 0 8
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ASM3P2508SP
rev 0.4
Clock Synthesizer and Frequency Generator with Peak EMI reduction
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Notice: The information in this document is subject to change without notice.
Ordering Information
Part Number
Marking
Package Type
Temperature
ASM3P2508SP-08ST
3P2508SP
8-Pin SOIC, TUBE
Commercial
ASM3P2508SP-08SR
3P2508SP
8-Pin SOIC, TAPE & REEL
Commercial
ASM3P2508SPF-08ST
3P2508SPF
8-Pin SOIC, TUBE, Pb free
Commercial
ASM3P2508SPF-08SR
3P2508SPF
8-Pin SOIC, TAPE & REEL, Pb free
Commercial
ASM3I2508SP-08ST
3I2508SP
8-Pin SOIC, TUBE
Industrial
ASM3I2508SP-08SR
3I2508SP
8-Pin SOIC, TAPE & REEL
Industrial
ASM3I2508SPF-08ST
3I2508SPF
8-Pin SOIC, TUBE, Pb free
Industrial
ASM3I2508SPF-08SR
3I2508SPF
8-Pin SOIC, TAPE & REEL, Pb free
Industrial
Device Ordering Information
A S M 3 P 2 5 0 8 S P F - 0 8 T R
Licensed under U.S Patent #s 5,488,627 and 5,631,921
OR - TSOT23 -6, T/R
SR - SOIC, T/R
TT TSSOP, TUBE
QR QFN, T/R
TR - TSSOP, T/R
QT - QFN, TRAY
VT TVSOP, TUBE
BT - BGA, TRAY
VR TVSOP, T/R
BR BGA, T/R
ST SOIC, TUBE UR - SOT-23,T/R
AR - SSOP, T/R DR - QSOP, T/R
AT SSOP, TUBE DT QSOP, TUBE
PIN COUNT
X = Automotive I = Industrial P or n/c = Commercial
(-40C to +125C) (-40C to +85C) (0C to +70C)
1 reserved
6 power management
2- Non PLL based
7 power management
3 EMI Reduction
8 power management
4 DDR support products
9 Hi performance
5 STD Zero Delay Buffer
0 - reserved
Alliance Semiconductor Mixed Signal Product
PART NUMBER
LEAD FREE PART
February 2005
ASM3P2508SP
rev 0.4
Clock Synthesizer and Frequency Generator with Peak EMI reduction
7 of 7
Notice: The information in this document is subject to change without notice.
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
Copyright 2004 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective
companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance
assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's
best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time,
without notice. If the product described herein is under development, significant changes to these specifications are possible.
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Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM3P2508SP
Document Version: v0.4
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