www.docs.chipfind.ru
June 2005
ASM2P20805A
rev 0.2
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V CMOS Dual 1-To-5 Clock Driver
Features
Advanced
CMOS
Technology
Guaranteed low skew < 200pS (max.)
Very low propagation delay < 2.5nS (max)
Very low duty cycle distortion < 270pS (max)
Very low CMOS power levels
Operating frequency up to 166MHz
TTL compatible inputs and outputs
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
V
CC
= 2.5V 0.2V
Available in SSOP and QSOP packages
Block Diagram
Functional Description
The ASM2P20805A is a 2.5V Clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in this document. The ASM2P20805A offers low
capacitance inputs. The ASM2P20805A is designed for
high speed clock distribution where signal quality and skew
are critical. The ASM2P20805A also allows single point-to-
point transmission line driving in applications such as
address distribution, where one signal must be distributed
to multiple receivers with low skew and high signal quality.
Pin Diagram
OB
1
OB
5
IN
A
IN
B
OE
B
OE
A
OA
1
OA
5
MON
5
5
V
CCB
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
MON
OE
B
IN
B
IN
A
OE
A
GND
Q
OA
5
OA
4
GND
A
OA
3
OA
2
OA
1
V
CCA
A
S
M
2
P
2
0
8
0
5
A
10 11
9 12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
1 20
June 2005
ASM2P20805A
rev 0.2
2.5V CMOS Dual 1-To-5 Clock Driver
2 of 11
Notice: The information in this document is subject to change without notice.
Pin Description
Pin #
Pin Names
Description
9,12
OE
A
, OE
B
3-State Output Enable Inputs (Active LOW)
10,11
IN
A
, IN
B
Clock
Inputs
2,3,4,6,7
OA
1
-OA
5
Clock
Outputs
19,18,17,15,14
OB
1
-OB
5
Clock
Outputs
1
V
CCA
Power supply for Bank A
20
V
CCB
Power supply for Bank B
5
GND
A
Ground for Bank A
16
GND
B
Ground for Bank B
8
GND
Q
Ground
13
MON Monitor
Output
Function Table
Inputs
Outputs
OE
A
, OE
B
IN
A
, IN
B
OA
n
, OB
n
MON
L L L L
L H H H
H L Z L
H H Z H
Note: H = HIGH; L = LOW; Z = High-Impedance
Capacitance
(T
A
= +25C, f = 1.0MHz)
Symbol
Parameter*
Conditions
Typ
Max
Unit
C
IN
Input
Capacitance
V
IN
= 0V
3
4
pF
C
OUT
Output
Capacitance
V
OUT
= 0V
-
6
pF
*This parameter is measured at characterization but not tested.
June 2005
ASM2P20805A
rev 0.2
2.5V CMOS Dual 1-To-5 Clock Driver
3 of 11
Notice: The information in this document is subject to change without notice.
Absolute Maximum Ratings
Symbol
Description
Max
Unit
V
CC
Input Power Supply Voltage
-0.5 to +4.6
V
V
I
Input Voltage
-0.5 to +5.5
V
V
O
Output Voltage
-0.5 to V
CC
+0.5 V
T
J
Junction
Temperature
150
C
T
s
Max. Soldering Temperature (10 sec)
260 C
T
STG
Storage Temperature
-65 to +165
C
T
DV
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics over Operating Range
Following Conditions Apply Unless Otherwise Specified
Industrial: T
A
= -40C to +85C, V
CC
= 2.5V 0.2V
Symbol
Parameter
Test Conditions
1
Min
Typ
2
Max
Unit
V
IH
Input HIGH Level
1.7
-
5.5
V
V
IL
Input LOW Level
-0.5
-
0.7
V
I
IH
Input HIGH Current
V
CC
= Max.
V
I
= 5.5V
-
-
1
I
IL
Input LOW Current
V
CC
= Max.
V
I
= GND
-
-
1
I
OZH
V
O
= V
CC
-
-
1
I
OZL
High Impedance Output Current
(3-State Outputs Pins)
V
CC
= Max.
V
O
= GND
-
-
1
A
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= -18mA
-
-0.7
-1.2
V
I
ODH
Output HIGH Current
V
CC
= 2.5V, V
IN
= V
IH
or V
IL
, V
O
= 1.25V
3,4
-15 -35
-90
mA
I
ODL
Output LOW Current
V
CC
= 2.5V, V
IN
= V
IH
or V
IL
, V
O
= 1.25V
3,4
25 55
100
mA
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
3,4
-30 -50
-120
mA
I
OH
= -8mA
1.7
5
- -
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= -100A
V
CC
- 0.2
-
-
V
I
OL
= 8mA
-
0.2
0.4
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 100A
-
-
0.2
V
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 2.5V, 25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
-0.6V at rated current.
June 2005
ASM2P20805A
rev 0.2
2.5V CMOS Dual 1-To-5 Clock Driver
4 of 11
Notice: The information in this document is subject to change without notice.
Power Supply Characteristics
Symbol
Parameter
Test Conditions
1
Min
Typ
2
Max
Unit
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply
Current
V
CC
= Max. V
IN
= GND or V
CC
-
0.1
20
A
I
CC
Power Supply Current per
Input HIGH
V
CC
= Max.
V
IN
= V
CC
0.6V
- 35
250
A
I
CCD
Dynamic Power Supply
Current per Output
3
V
CC
= Max.
C
L
= 15pF
All Outputs Toggling
V
IN
= V
CC
V
IN
= GND
- 65
100
A/MHz
V
IN
= V
CC
V
IN
= GND
- 100
125
V
CC
= Max.
C
L
= 15pF
All Outputs Toggling
f
i
= 133MHz
V
IN
= V
CC
0.6V
V
IN
= GND
- 100
125
V
IN
= V
CC
V
IN
= GND
- 115
150
I
C
Total Power Supply
Current
4
V
CC
= Max.
C
L
= 15pF
All Outputs Toggling
f
i
= 166MHz
V
IN
= V
CC
0.6V
V
IN
= GND
- 115
150
mA
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 2.5V, +25C ambient.
3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
4. I
C
= IQUIESCENT + IINPUTS + IDYNAMIC
I
C
= I
CC
+ I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= V
CC
-0.6V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
NO = Number of Outputs at f
O
June 2005
ASM2P20805A
rev 0.2
2.5V CMOS Dual 1-To-5 Clock Driver
5 of 11
Notice: The information in this document is subject to change without notice.
Switching Characteristics Over Operating Range
3,4
Symbol
Parameter
Conditions
1
Min
2
Max
Unit
t
PLH
t
PHL
Propagation Delay
IN
A
to OA
n
, IN
B
to OB
n
1 3
nS
t
R
Output Rise Time
(Measured from 0.8V to 2V)
- 1.5
nS
t
F
Output Fall Time
(Measured from 2V to 0.8V)
- 1.5
nS
t
SK(O)
Same device output pin to pin skew
5
- 270
pS
t
SK(P)
Pulse skew
6,9
- 270
pS
t
SK(PP)
Part to part skew
7
- 550
pS
t
PZL
t
PZH
Output Enable Time
OE
A
to OA
n
, OE
B
to OB
n
- 5.2
nS
t
PLZ
t
PHZ
Output Disable Time
OE
A
to OA
n
, OE
B
to OB
n
- 5.2
nS
f
MAX
Input
Frequency
C
L
= 15pF
f 133MHz
- 133
MHz
t
PLH
t
PHL
Propagation Delay
IN
A
to OA
n
, INB to OB
n
0.5 2.5
nS
t
R
Output Rise Time
(Measured from 0.7V to 1.7V)
- 1.25
nS
t
F
Output Fall Time
(Measured from 1.7V to 0.7V)
- 1.25
nS
t
SK(O)
Same device output pin to pin skew
5
- 200
pS
t
SK(P)
Pulse skew
6,9
- 270
pS
t
SK(PP)
Part to part skew
7
- 550
pS
t
PZL
t
PZH
Output Enable Time
OE
A
to OA
n
, OE
B
to OB
n
- 5.2
nS
t
PLZ
t
PHZ
Output Disable Time
OE
A
to OA
n
, OE
B
to OB
n
- 5.2
nS
f
MAX
Input
Frequency
C
L
= 15pF
133MHz f 166MHz
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