March 2001
Copyright Alliance Semiconductor. All rights reserved.
AS7C513
AS7C3513
5V/3.3V 32K16 CMOS SRAM
3/23/01; v.1.0
Alliance Semiconductor
P. 1 of 10
Features
AS7C513 (5V version)
AS7C3513 (3.3V version)
Industrial and commercial temperature
Organization: 32,768 words 16 bits
Center power and ground pins
High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
Low power consumption: ACTIVE
- 800 mW (AS7C513) / max @ 12 ns
- 432 mW (AS7C3513) / max @ 12 ns
Low power consumption: STANDBY
- 28 mW (AS7C513) / max CMOS
- 18 mW (AS7C3513) / max CMOS
2.0V data retention
Easy memory expansion with CE, OE inputs
TTL-compatible, three-state I/O
44-pin JEDEC standard package
- 400 mil SOJ
- 400 mil TSOP II
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
32K 16
Array
OE
CE
WE
Column decoder
R
o
w
dec
oder
A0
A1
A2
A3
A4
A5
A7
V
CC
GND
A8
A9
A10
A11
A12
A13
A14
Control circuit
I/O0I/O7
I/O8I/O15
UB
LB
I/O
buffer
A6
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
44-Pin SOJ, TSOP II (400 mil)
21
22
A11
NC
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A5
A6
OE
A4
A
S
7C513
A
S
7C3513
Selection guide
Shaded areas indicate advance information.
AS7C513-12
AS7C3513-12
AS7C513-15
AS7C3513-15
AS7C513-20
AS7C3513-20
Unit
Maximum address access time
12
15
20
ns
Maximum output enable access time
5
7
9
ns
Maximum operating current
AS7C513
160
150
140
mA
AS7C3513
120
110
100
mA
Maximum CMOS standby current
AS7C513
5
5
5
mA
AS7C3513
5
5
5
mA
AS7C513
AS7C3513
3/23/01; v.1.0
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C513 and the AS7C3513 are high performance CMOS 524,288-bit Static Random Access Memory (SRAM) devices organized as
32,768 words 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12/15/20 ns with output enable access times (t
OE
) of 6,7,8 ns are ideal for high
performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high, the devices enter standby mode. The AS7C513 and AS7C3513 are guaranteed not to exceed 28/18 mW power
consumption in CMOS standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0-I/O7,
and/or I/O8I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0I/O7, and UB controls the higher bits, I/O8I/O15.
All chip inputs and outputs are TTL-compatible. The AS7C513 and AS7C3513 are packaged in common industry standard packages.
Absolute maximum ratings
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don't care; L = Low; H = High
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
AS7C513
V
t1
0.50
+7.0
V
AS7C3513
V
t1
0.50
+5.0
V
Voltage on any pin relative to GND
V
t2
0.50
V
CC
+0.50
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
o
C
Ambient temperature with V
CC
applied
T
bias
55 +125
o
C
DC current into outputs (low)
I
OUT
50
mA
CE
WE
OE
LB
UB
I/O0I/O7
I/O8I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (I
SB
, I
SBI
)
L
H
L
L
H
D
OUT
High Z
Read I/O0I/O7 (I
CC
)
L
H
L
H
L
High Z
D
OUT
Read I/O8I/O15 (I
CC
)
L
H
L
L
L
D
OUT
D
OUT
Read I/O0I/O15 (I
CC
)
L
L
X
L
L
D
IN
D
IN
Write I/O0I/O15 (I
CC
)
L
L
X
L
H
D
IN
High Z
Write I/O0I/O7 (I
CC
)
L
L
X
H
L
High Z
D
IN
Write I/O8I/O15 (I
CC
)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (I
CC
)
AS7C513
AS7C3513
3/23/01; v.1.0
Alliance Semiconductor
P. 3 of 10
Recommended operating conditions
V
IL
min = 3.0V for pulse width less than t
RC
/2.
DC operating characteristics (over the operating range)
1
Shaded areas indicate advance information.
Capacitance (f = 1MHz, T
a
= 25
o
C, V
CC
= NOMINAL)
2
Parameter
Device
Symbol
Min
Typical
Max
Unit
Supply voltage
AS7C513
V
CC
4.5
5.0
5.5
V
AS7C3513
V
CC
3.0
3.3
3.6
V
Input voltage
AS7C513
V
IH
2.2
V
CC
+ 0.5
V
AS7C3513
V
IH
2.0
V
CC
+ 0.5
V
IL
0.5
0.8
V
Ambient operating temperature
commercial
T
A
0
70
C
industrial
T
A
40
05
C
Parameter
Symbol
Test conditions
Device
-12
-15
-20
Unit
Min Max Min Max Min Max
Input leakage current
|
I
LI
|
V
CC
= Max
V
IN
= GND to V
CC
1
1
1
A
Output leakage current
|
I
LO
|
V
CC
= Max
V
OUT
= GND to V
CC
1
1
1
A
Operating power supply
current
I
CC
V
CC
= Max, CE
V
IL
f = f
Max
, I
OUT
= 0mA
AS7C513
160
150
140
mA
AS7C3513
120
110
100
Standby power supply
current
I
SB
V
CC
= Max, CE
V
IL
f = f
Max
, I
OUT
= 0mA
AS7C513
40
40
40
mA
AS7C3513
40
40
40
I
SB1
V
CC
=
Max, CE
V
CC
0.2V
V
IN
GND + 0.2V or
V
IN
V
CC
0.2V, f = 0
AS7C513
3
3
3
mA
AS7C3513
3
3
3
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
V
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE, LB, UB
V
in
= 0V
5
pF
I/O capacitance
C
I/O
I/O
V
in
= V
out
= 0V
7
pF
AS7C513
AS7C3513
3/23/01; v.1.0
Alliance Semiconductor
P. 4 of 10
Read cycle (over the operating range)
3,9
Shaded areas indicate advance information.
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CE, OE, UB, LB controlled)
3,6,8,9
Parameter
Symbol
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
12
15
20
ns
Address access time
t
AA
12
15
20
ns
3
Chip enable (CE) access time
t
ACE
12
15
20
ns
3
Output enable (OE) access time
t
OE
6
7
8
ns
Output hold from address change
t
OH
3
4
4
ns
5
CE Low to output in low Z
t
CLZ
0
0
0
ns
4, 5
CE High to output in high Z
t
CHZ
6
7
8
ns
4, 5
OE Low to output in low Z
t
OLZ
0
0
0
ns
4, 5
Byte select access time
t
BA
6
7
8
ns
Byte select Low to low Z
t
BLZ
0
0
0
ns
4,5
Byte select High to high Z
t
BHZ
6
7
9
ns
4,5
OE High to output in high Z
t
OHZ
6
7
9
ns
4, 5
Power up time
t
PU
0
0
0
ns
4, 5
Power down time
t
PD
12
15
20
ns
4, 5
Undefined output/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data OUT
Address
Data valid
Previous data valid
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data OUT
AS7C513
AS7C3513
3/23/01; v.1.0
Alliance Semiconductor
P. 5 of 10
Write cycle (over the operating range)
11
Shaded areas indicate advance information.
Write waveform 1(WE controlled)
10,11
Write waveform 2 (CE controlled)
10,11
Parameter
Symbol
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
12
15
20
ns
Chip enable (CE) to write end
t
CW
9
10
12
ns
Address setup to write end
t
AW
8
10
12
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
8
10
12
ns
Address hold from end of write
t
AH
0
0
0
ns
Data valid to write end
t
DW
6
8
10
ns
Data hold time
t
DH
0
0
0
ns
5
Write enable to output in high Z
t
WZ
6
7
9
ns
4, 5
Output active from write end
t
OW
3
3
3
ns
4, 5
Byte select Low to end of write
t
BW
8
9
12
ns
Address
LB, UB
WE
Data IN
Data OUT
t
WC
t
BW
t
AW
t
AS
t
WP
t
DW
t
DH
t
OW
t
WZ
Data undefined
High-Z
Data valid
Address
CE
LB, UB
WE
Data IN
t
WC
t
CW
t
BW
t
WP
t
DW
t
DH
t
OW
t
WZ
t
AH
Data OUT
Data undefined
High-Z
High-Z
t
AS
t
AW
Data valid
t
CLZ
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