Document Outline
- Features
- Pin arrangements
- Selection guide
- Absolute maximum ratings
- Truth table
- Recommended operating condition
- .
- DC operating characteristics (over the operating range)1
- Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)4
- Read cycle (over the operating range)2,8
- Key to switching waveforms
- Read waveform 1 (address controlled)2,5,6,8
- Read waveform 2 (CE, OE controlled)2,5,7,8
- Write cycle (over the operating range)9
- Write waveform 1 (WE controlled)9
- Write waveform 2 (CE controlled)9
- AC test conditions
- Package dimensions
- Ordering codes
- Part numbering system
- Revision History
May 2005
Preliminary
Copyright Alliance Semiconductor. All rights reserved.
AS7C4096A
5.0V 512K 8 CMOS SRAM
5/27/05, v. 1.1
Alliance Semiconductor
P. 1 of 10
Features
Pin compatible to AS7C4096
Industrial and commercial temperature
Organization: 524,288 words 8 bits
Center power and ground pins
High speed
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
Low power consumption: ACTIVE
- 880mW/max @ 10 ns
Low power consumption: STANDBY
- 55mW/max CMOS
Equal access and cycle times
Easy memory expansion with CE, OE inputs
TTL-compatible, three-state I/O
JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
524,288 8
Array
(4,194,304)
Se
ns
e a
m
p
Input buffer
I/O8
I/O1
OE
CE
WE
Column decoder
R
o
w decoder
Control
Circuit
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
A1
7
A1
8
A9
Pin arrangement
s
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
17
18
A8
A9
36
35
34
33
NC
A18
A17
A16
GND
V
CC
I/O6
I/O5
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
I/O8
I/O7
A1
A2
A3
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A16
A15
A17
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
3
4
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
OE
A18
36-pin SOJ (400 mil)
44-pin TSOP 2
Selection guide
10
12
15
20
Unit
Maximum address access time
10
12
15
20
ns
Maximum outputenable access time
5
6
6
6
ns
Maximum operating current
160
140
120
100
mA
Maximum CMOS standby current
10
10
10
10
mA
AS7C4096A
5/27/05, v. 1.1
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS
standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as
per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
V
t1
0.5
+7.0
V
Voltage on any pin relative to GND
V
t2
0.5
V
CC
+0.5
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
C
Temperature with V
CC
applied
T
bias
55
+125
C
DC current into output (low)
I
OUT
20
mA
Truth table
CE
WE
OE
Data
Mode
H
X
X
High Z
Standby (I
SB
, I
SB1
)
L
H
H
High Z
Output disable (I
CC
)
L
H
L
D
OUT
Read (I
CC
)
L
L
X
D
IN
Write (I
CC
)
AS7C4096A
5/27/05, v. 1.1
Alliance Semiconductor
P. 3 of 10
*V
IH
max = V
CC
+ 1.5V for pulse width less than 5 nS.
**V
IL
min = 1.0V for pulse width less than 5 nS.
.
Recommended operating condition
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
CC
(10/12/15/20)
4.5
5.0
5.5
V
Input voltage
V
IH
*
2.2
V
CC
+ 0.5
V
V
IL
**
0.5
0.8
V
Ambient operating
temperature
commercial
T
A
0
70
C
industrial
T
A
40
85
C
DC operating characteristics (over the operating range)
1
Parameter
Symbol
Test conditions
10
12
15
20
Unit Notes
Min Max Min Max Min Max Min Max
Input leakage
current
|I
LI
|
V
CC
= Max, V
IN
= GND to V
CC
1
1
1
1
A
Output leakage
current
|I
LO
|
V
CC
= Max, CE = V
IH
V
OUT
= GND to V
CC
1
1
1
1
A
Operating power
supply current
I
CC
V
CC
= Max, CE < V
IL
f = f
Max
, I
OUT
= 0mA
160
140
120
100
mA
Standby power
supply current
I
SB
V
CC
= Max, CE > V
IH
f = f
Max
, I
OUT
= 0mA
60
55
50
40
mA
I
SB1
V
CC
= Max,
CE
V
CC
0.2V,
V
IN
0.2V or V
IN
V
CC
0.2V,
f = 0
10
10
10
10
mA
Output voltage
V
OL
I
OL
= 6 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
4
I
OL
= 8 mA, V
CC
= Min
0.5
0.5
0.5
0.5
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
4
C
apacitance (f = 1MHz, T
a
= 25
C, V
CC
= NOMINAL)
4
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE
V
IN
= 0V
5
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0V
7
pF
AS7C4096A
5/27/05, v. 1.1
Alliance Semiconductor
P. 4 of 10
Key to switching waveforms
Read waveform 1 (address controlled)
2,5,6,8
Read waveform 2 (CE, OE controlled)
2,5,7,8
Read cycle (over the operating range)
2,8
Parameter
Symbol
10
12
15
20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
2
Chip enable (CE) access time
t
ACE
10
12
15
20
ns
2
Output enable (OE) access time
t
OE
5
6
6
6
ns
Output hold from address change
t
OH
3
3
3
3
ns
4
CE Low to output in low Z
t
CLZ
3
3
3
3
ns
3,4
CE High to output in high Z
t
CHZ
5
6
7
9
ns
3,4
OE Low to output in low Z
t
OLZ
0
0
0
0
ns
3,4
OE High to output in high Z
t
OHZ
5
6
7
9
ns
3,4
Power up time
t
PU
0
0
0
0
ns
3,4
Power down time
t
PD
10
12
15
20
ns
3,4
Undefined/don't care
Falling input
Rising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50%
50%
t
OHZ
Data valid
t
RC1
CE
AS7C4096A
5/27/05, v. 1.1
Alliance Semiconductor
P. 5 of 10
Write waveform 1 (WE controlled)
9
Write cycle (over the operating range)
9
Parameter
Symbol
10
12
15
20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
10
12
15
20
ns
Chip enable (CE) to write end
t
CW
7
8
10
12
ns
Address setup to write end
t
AW
7
8
10
12
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width (OE = high)
t
WP1
7
8
10
12
ns
Write pulse width (OE = low
t
WP2
10
12
15
20
ns
Address hold from end of write
t
AH
0
0
0
0
ns
Write recovery time
t
WR
0
0
0
0
ns
Data valid to write end
t
DW
5
6
7
9
ns
Data hold time
t
DH
0
0
0
0
ns
3,4
Write enable to output in high Z
t
WZ
2
5
2
6
2
7
2
9
ns
3,4
Output active from write end
t
OW
3
3
3
3
ns
3,4
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
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