January 2005
Copyright Alliance Semiconductor. All rights reserved.
AS7C4096
AS7C34096
5V/3.3V 512K 8 CMOS SRAM
1/13/05; v.1.9
Alliance Semiconductor
P. 1 of 9
Features
AS7C4096 (5V version)
AS7C34096 (3.3V version)
Industrial and commercial temperature
Organization: 524,288 words 8 bits
Center power and ground pins
High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
Equal access and cycle times
Easy memory expansion with CE, OE inputs
TTL-compatible, three-state I/O
JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
ESD protection
2000 volts
Latch-up current
100 mA
Logic block diagram
524,288 8
Array
(4,194,304)
S
e
ns
e am
p
Input buffer
I/O8
I/O1
OE
CE
WE
Column decoder
Row decoder
Control
Circuit
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
A10 A1
1
A12 A13 A14 A15 A16 A17 A18
A9
Pin arrangement
s
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
17
18
A8
A9
36
35
34
33
NC
A18
A17
A16
GND
V
CC
I/O6
I/O5
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
I/O8
I/O7
A1
A2
A3
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A16
A15
A17
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
3
4
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
OE
A18
36-pin SOJ (400 mil)
44-pin TSOP 2
Selection guide
10
12
15
20
Unit
Maximum address access time
10
12
15
20
ns
Maximum outputenable access time
5
6
7
8
ns
Maximum operating current
AS7C4096
250
220
180
mA
AS7C34096
160
130
110
100
mA
Maximum CMOS standby current
AS7C4096
20
20
20
mA
AS7C34096
20
20
20
20
mA
AS7C4096
AS7C34096
1/13/05; v.1.9
Alliance Semiconductor
P. 2 of 9
Functional description
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 524,288 words 8 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5/6/7/8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The AS7C4096/AS7C34096 is guaranteed not to exceed 110/72 mW power
consumption in CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1I/O8 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from either a single 5V(AS7C4096) or 3.3V(AS7C34096)
supply. Both devices are available in the JEDEC standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Key: X = Don't care, L = Low, H = High
Absolute maximum ratings
Parameter
Device
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
AS7C4096
V
t1
1
+7.0
V
AS7C34096
V
t1
0.5
+5.0
V
Voltage on any pin relative to GND
V
t2
0.5
V
CC
+0.5
V
Power dissipation
P
D
1.0
W
Storage temperature
T
stg
65
+150
C
Temperature with V
CC
applied
T
bias
55
+125
C
DC current unto output (low)
I
OUT
20
mA
Truth table
CE
WE
OE
Data
Mode
H
X
X
High Z
Standby (I
SB
, I
SB1
)
L
H
H
High Z
Output disable (I
CC
)
L
H
L
D
OUT
Read (I
CC
)
L
L
X
D
IN
Write (I
CC
)
AS7C4096
AS7C34096
1/13/05; v.1.9
Alliance Semiconductor
P. 3 of 9
Recommended operating condition
Parameter
Device
Symbol
Min
Nominal
Max
Unit
Supply voltage
AS7C4096
V
CC
(12/15/20)
4.5
5.0
5.5
V
AS7C34096
V
CC
(10)
3.15
3.30
3.6
V
AS7C34096
V
CC
(12/15/20)
3.0
3.3
3.6
V
Input voltage
AS7C4096
V
IH
2.2
V
CC
+ 0.5
V
AS7C34096
V
IH
2.0
V
CC
+ 0.5
V
V
IL
1
1 V
IL
min = 1.0V for pulse width less than 5ns.
0.5
0.8
V
Ambient operating
temperature
commercial
T
A
0
70
C
industrial
T
A
40
85
C
DC operating characteristics (over the operating range)
1
Parameter Symbol
Test conditions
Device
10
12
15
20
Unit
Min Max Min Max Min Max Min Max
Input leakage
current
|I
LI
|
V
CC
= Max, V
IN
= GND to V
CC
AS7C4096/
AS7C34096
1
1
1
1
A
Output
leakage
current
|I
LO
|
V
CC
= Max, CE = V
IH
V
OUT
= GND to V
CC
AS7C4096/
AS7C34096
1
1
1
1
A
Operating
power supply
current
I
CC
V
CC
= Max, CE < V
IL
f = f
Max
, I
OUT
= 0mA
AS7C4096
250
220
180 mA
AS7C34096
160
130
110
100
Standby
power supply
current
I
SB
V
CC
= Max, CE = V
IH
f = f
Max
, I
OUT
= 0mA
AS7C4096
60
60
60
mA
AS7C34096
60
60
60
60
I
SB1
V
CC
= Max,
CE
V
CC
0.2V, V
IN
0.2V or V
IN
V
CC
0.2V, f = 0
AS7C4096
20
20
20
mA
AS7C34096
20
20
20
20
Output
voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
AS7C4096/
AS7C34096
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
C
apacitance (f = 1MHz, T
A
= 25
C, V
CC
= NOMINAL)
2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE
V
IN
= 0V
5
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0V
7
pF
AS7C4096
AS7C34096
1/13/05; v.1.9
Alliance Semiconductor
P. 4 of 9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CE, OE controlled)
3,6,8,9
Read cycle (over the operating range)
3,9
Parameter
Symbo
l
10
12
15
20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
3
Chip enable (CE) access time
t
ACE
10
12
15
20
ns
3
Output enable (OE) access time
t
OE
5
6
7
8
ns
Output hold from address change
t
OH
3
3
3
3
ns
5
CE Low to output in low Z
t
CLZ
3
3
0
0
ns
4, 5
CE High to output in high Z
t
CHZ
5
6
7
9
ns
4, 5
OE Low to output in low Z
t
OLZ
0
0
0
0
ns
4, 5
OE High to output in high Z
t
OHZ
5
6
7
9
ns
4, 5
Power up time
t
PU
0
0
0
0
ns
4, 5
Power down time
t
PD
10
12
15
20
ns
4, 5
Undefined/don't care
Falling input
Rising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50%
50%
t
OHZ
Data valid
t
RC1
CE
AS7C4096
AS7C34096
1/13/05; v.1.9
Alliance Semiconductor
P. 5 of 9
Write waveform 1 (WE controlled)
10,11
Write waveform 2 (CE controlled)
10,11
Write cycle (over the operating range)
11
Parameter
Symbol
10
12
15
20
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
10
12
15
20
ns
Chip enable (CE) to write end
t
CW
7
8
10
12
ns
Address setup to write end
t
AW
7
8
10
12
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width (OE = high)
t
WP1
7
8
10
12
ns
Write pulse width (OE = low
t
WP2
10
12
15
20
ns
Address hold from end of write
t
AH
0
0
0
0
ns
Write recovery time
t
WR
0
0
0
0
ns
Data valid to write end
t
DW
5
6
7
9
ns
Data hold time
t
DH
0
0
0
0
ns
4, 5
Write enable to output in high Z
t
WZ
0
5
0
6
0
7
0
9
ns
4, 5
Output active from write end
t
OW
3
3
3
3
ns
4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
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