March 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C3513B
3.3V 32K16 CMOS SRAM
3/24/04, v.1.2
Alliance Semiconductor
P. 1 of 10
Features
Industrial and commercial temperature
Organization: 32,768 words 16 bits
Center power and ground pins
High speed
10/12/15/20 ns address access time
5, 6, 7, 8 ns output enable access time
Low power consumption: ACTIVE
288 mW / max @ 10 ns
Low power consumption: STANDBY
18 mW / max CMOS
6T 0.18m CMOS Technology
Easy memory expansion with CE, OE inputs
TTL-compatible, three-state I/O
44-pin JEDEC standard package
400 mil SOJ
400 mil TSOP 2
ESD protection > 2000 volts
Latch-up current > 200 mA
Logic block diagram
32K 16
Array
OE
CE
WE
Column decoder
Row decoder
A0
A1
A2
A3
A4
A5
A7
V
CC
GND
A8
A9
A10
A1
1
A12
A13
A14
Control circuit
I/O0I/O7
I/O8I/O15
UB
LB
I/O
buffer
A6
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
44-Pin SOJ, TSOP 2 (400 mil)
21
22
A11
NC
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A5
A6
OE
A4
AS7C351
3B
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
80
75
70
65
mA
Maximum CMOS standby current
5
5
5
5
mA
AS7C3513B
3/24/04, v.1.2
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C3513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words 16
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns are ideal for
high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device consumes I
SB
power. If the bus is static, then the full
standby power is reached (I
SB1
). The AS7C3513B is guaranteed not to exceed 18mW power consumption under nominal full standby
conditions.
A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0 - I/O7,
and/or I/O8 I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 I/O7, and UB controls the higher bits, I/O8 I/O15.
All chip inputs and outputs are TTL-compatible. The AS7C3513B is packaged in common industry standard packages.
Absolute maximum ratings
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don't care; L = Low; H = High
Parameter
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
V
t1
0.50
+5.0
V
Voltage on any pin relative to GND
V
t2
0.50
V
CC
+0.50
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
o
C
Ambient temperature with V
CC
applied
T
bias
55 +125
o
C
DC current into outputs (low)
I
OUT
20
mA
CE
WE
OE
LB
UB
I/O0I/O7
I/O8I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (I
SB
, I
SBI
)
L
H
L
L
H
D
OUT
High Z
Read I/O0I/O7 (I
CC
)
L
H
L
H
L
High Z
D
OUT
Read I/O8I/O15 (I
CC
)
L
H
L
L
L
D
OUT
D
OUT
Read I/O0I/O15 (I
CC
)
L
L
X
L
L
D
IN
D
IN
Write I/O0I/O15 (I
CC
)
L
L
X
L
H
D
IN
High Z
Write I/O0I/O7 (I
CC
)
L
L
X
H
L
High Z
D
IN
Write I/O8I/O15 (I
CC
)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (I
CC
)
AS7C3513B
3/24/04, v.1.2
Alliance Semiconductor
P. 3 of 10
Recommended operating conditions
V
IL
= -1.0V for pulse width less than 5ns
V
IH =
V
CC
+ 1.5V for pulse width less than 5ns
DC operating characteristics (over the operating range)
1
Capacitance (f = 1MHz, T
a
= 25
o
C, V
CC
= NOMINAL)
2
Parameter
Symbol
Min
Typical
Max
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
Input voltage
V
IH
2.0
V
CC
+ 0.5
V
IL
0.5
0.8
V
Ambient operating temperature
commercial
T
A
0
70
C
industrial
T
A
40
85
C
Parameter
Sym
Test conditions
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Input leakage
current
| I
LI
|
V
CC
= Max
V
IN
= GND to V
CC
1
1
1
1
A
Output leakage
current
| I
LO
|
V
CC
= Max
V
OUT
= GND to V
CC
1
1
1
1
A
Operating
power supply
current
I
CC
V
CC
= Max, CE V
IL
f = f
Max
, I
OUT
= 0mA
80
75
70
65
mA
Standby power
supply current
I
SB
V
CC
= Max, CE V
IH
f = f
Max
30
25
20
20
mA
I
SB1
V
CC
= Max, CE V
CC
0.2V
V
IN
0.2V or V
IN
V
CC
0.2V,
f = 0
5
5
5
5
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
V
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE, LB, UB
V
in
= 0V
5
pF
I/O capacitance
C
I/O
I/O
V
in
= V
out
= 0V
7
pF
AS7C3513B
3/24/04, v.1.2
Alliance Semiconductor
P. 4 of 10
Read cycle (over the operating range)
3,9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
10
12
15
20
ns
Address access time
t
AA
10
12
15
20
ns
3
Chip enable (CE) access time
t
ACE
10
12
15
20
ns
3
Output enable (OE) access time
t
OE
5
6
7
8
ns
Output hold from address
change
t
OH
3
3
3
3
ns
5
CE low to output in low Z
t
CLZ
3
3
3
3
ns
4 , 5
CE high to output in high Z
t
CHZ
3
3
4
5
ns
4 , 5
OE low to output in low Z
t
OLZ
0
0
0
0
ns
4 , 5
Byte select access time
t
BA
5
6
7
8
ns
Byte select Low to low Z
t
BLZ
0
0
0
0
ns
4 , 5
Byte select High to high Z
t
BHZ
5
6
6
8
ns
4 , 5
OE high to output in high Z
t
OHZ
5
6
7
8
ns
4 , 5
Power up time
t
PU
0
0
0
0
ns
4 , 5
Power down time
t
PD
10
12
15
20
ns
4 , 5
Undefined output/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data OUT
Address
Data valid
Previous data valid
AS7C3513B
3/24/04, v.1.2
Alliance Semiconductor
P. 5 of 10
Read waveform 2 (CE, OE, UB, LB controlled)
3,6,8,9
Write cycle (over the operating range)
11
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
10
12
15
20
ns
Chip enable (CE) to write end
t
CW
8
9
10
12
ns
Address setup to write end
t
AW
8
9
10
12
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width
t
WP
7
8
9
12
ns
Write recovery time
t
WR
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
ns
Data valid to write end
t
DW
5
6
8
10
ns
Data hold time
t
DH
0
0
0
0
ns
5
Write enable to output in high
Z
t
WZ
5
6
7
8
ns
4 , 5
Output active from write end
t
OW
1
1
1
2
ns
4 , 5
Byte select low to end of write
t
BW
7
8
9
9
ns
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data OUT
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