November 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 1 of 19
3.3V 256K32/36 Pipelined burst Synchronous SRAM with NTD
TM
Features
Organization: 262,144 words 32 or 36 bits
NTD
TM
architecture for efficient bus operation
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous operation
Common data inputs and data outputs
Asynchronous output enable control
Available in 100-pin TQFP
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3 core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic Block Diagram
Selection Guide
-166
-133
Units
Minimum cycle time
6
7.5
ns
Maximum clock frequency
166
133
MHz
Maximum clock access time
3.5
4
ns
Maximum operating current
475
400
mA
Maximum standby current
130
100
mA
Maximum CMOS standby current (DC)
30
30
mA
W
r
ite B
u
f
f
er
Address
D
Q
CLK
register
Output
Register
DQ[a:d]
36/32
36/32
18
18
CLK
CE0
CE1
CE2
A[17:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
36/32
36/32
36/32
OE
256K x 32/36
SRAM
Array
R/W
DQ [a:d]
BWa
BWc
BWb
BWd
CLK
Q
D
ADV / LD
LBO
Burst logic
addr. registers
Write delay
36/32
18
ZZ
CLK
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 2 of 19
8 Mb Synchronous SRAM products
list
1,2
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD
:
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT
:
Flow-through Burst Synchronous SRAM
NTD
1
-PL
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
:
Flow-through Burst Synchronous SRAM with NTD
TM
Org
Part Number
Mode
Speed
512KX18
AS7C33512PFS18A
PL-SCD
166/133 MHz
256KX32
AS7C33256PFS32A
PL-SCD
166/133 MHz
256KX36
AS7C33256PFS36A
PL-SCD
166/133 MHz
512KX18
AS7C33512PFD18A
PL-DCD
166/133 MHz
256KX32
AS7C33256PFD32A
PL-DCD
166/133 MHz
256KX36
AS7C33256PFD36A
PL-DCD
166/133 MHz
512KX18
AS7C33512FT18A
FT
7.5/8.5/10 ns
256KX32
AS7C33256FT32A
FT
7.5/8.5/10 ns
256KX36
AS7C33256FT36A
FT
7.5/8.5/10 ns
512KX18
AS7C33512NTD18A
NTD-PL
166/133 MHz
256KX32
AS7C33256NTD32A
NTD-PL
166/133 MHz
256KX36
AS7C33256NTD36A
NTD-PL
166/133 MHz
512KX18
AS7C33512NTF18A
NTD-FT
7.5/8.5/10 ns
256KX32
AS7C33256NTF32A
NTD-FT
7.5/8.5/10 ns
256KX36
AS7C33256NTF36A
NTD-FT
7.5/8.5/10 ns
1. NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 3 of 19
Pin arrangement for TQFP (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LB
O A A A A A1 A0 NC NC V
SS
V
DD
NC NC
A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE0 CE1 BWd BWc BWb BW
a
CE2 V
DD
V
SS
CLK R/W CEN OE ADV/
LD
NC
A
A A
TQFP 14x20mm
A
DQPc/NC
DQc0
DQc1
V
DDQ
V
SSQ
DQc2
DQc3
DQc4
DQc5
V
SSQ
V
DDQ
DQc6
DQc7
NC
V
DD
NC
V
SS
DQd0
DQd1
V
DDQ
V
SSQ
DQd2
DQd3
DQd4
DQd5
V
SSQ
V
DDQ
DQd6
DQd7
DQPd/NC
DQPb/NC
DQb7
DQb6
V
DDQ
V
SSQ
DQb5
DQb4
DQb3
DQb2
V
SSQ
V
DDQ
DQb1
DQb0
V
ss
ZZ
DQa7
DQa6
V
DDQ
V
SSQ
DQa5
DQa4
DQa3
DQa2
V
SSQ
V
DDQ
DQa1
DQa0
DQP/NC
V
DD
NC
Note: Pins 1, 30, 51 , and 80 are NC for 32
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 4 of 19
Functional description
The AS7C33256NTD32/36A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized
as 262,144 words 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD
TM
) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for
valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or
read-modify-write operations.
NTD
TM
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle
flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
NTD
TM
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined
mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select,
R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations,
including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33256NTD36A and AS7C33256NTD32A operate with a 3.3V 5% power supply for the device core (V
DD
). DQ circuits use a
separate power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 1420 mm TQFP package
*Guaranteed not tested
TQFP thermal resistance
Capacitance
Parameter
Symbol
Test conditions
Min
Max
Unit
Input capacitance
C
IN
*
V
in
= 0V
-
5
pF
I/O capacitance
C
I/O
*
V
in
= V
out
= 0V
-
7
pF
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)
1
1 This parameter is sampled
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1layer
JA
40
C/W
4layer
JA
22
C/W
Thermal resistance
(junction to top of case)
1
JC
8
C/W
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 5 of 19
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The
duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs
except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed
to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations
are completed. Similarly, when exiting SNOOZE MODE during t
PUS
, only a DESELECT or READ cycle should be given while
the SRAM is transitioning out of SNOOZE MODE.
Signal descriptions
Signal
I/O Properties Description
CLK
I
CLOCK
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
I
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1
I
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b,c,d]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
ADV/LD
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
R/W
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
BW[a,b,c,d]
I
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
ZZ
I
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
-
No connect. Note that pin 84 will be used for future address expansion to 16Mb density.
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 6 of 19
Synchronous truth table
[5,6,7,8,9
]
Key: X = Don't Care, H = HIGH, L = LOW.
BWn = H means all byte write signals (BWa, BWb, BW
c, and
BW
d) are HIGH.
BW
n = L means one or
more byte write signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application's requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus
will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
BW
a enables WRITEs to byte "a" (DQa pins/balls);
BW
b enables WRITEs to byte "b" (DQb pins/balls);
BW
c enables WRITEs to byte "c" (DQc pins/
balls);
BW
d enables WRITEs to byte "d" (DQd pins/balls).
6 All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting
CEN
HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low in this truth table.
Burst Order
Interleaved Burst Order (LBO=1)
Linear Burst Order (LBO=0)
A1 A0 A1 A0 A1 A0 A1 A0
A1 A0 A1 A0 A1 A0 A1 A0
Starting Address
0 0
0 1
1 0
1 1
Starting Address
0 0
0 1
1 0
1 1
First increment
0 1
0 0
1 1
1 0
First increment
0 1
1 0
1 1
0 0
Second increment
1 0
1 1
0 0
0 1
Second increment
1 0
1 1
0 0
0 1
Third increment
1 1
1 0
0 1
0 0
Third increment
1 1
0 0
0 1
1 0
CE0 CE1 CE2 ADV/LD R/W
BWn
OE CEN
Address
source
CLK
Operation
DQ
Notes
H
X
X
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
X
H
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
L
X
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
X
X
H
X
X
X
L
NA
L to H
CONTINUE DESELECT Cycle
High-Z
1
L
H
L
L
H
X
L
L
External L to H
READ Cycle (Begin Burst)
Q
X
X
X
H
X
X
L
L
Next
L to H
READ Cycle (Continue Burst)
Q
1,10
L
H
L
L
H
X
H
L
External L to H NOP/DUMMY READ (Begin Burst) High-Z
2
X
X
X
H
X
X
H
L
Next
L to H
DUMMY READ (Continue Burst)
High-Z 1,2,10
L
H
L
L
L
L
X
L
External L to H
WRITE CYCLE (Begin Burst)
D
3
X
X
X
H
X
L
X
L
Next
L to H
WRITE CYCLE (Continue Burst)
D
1,3,10
L
H
L
L
L
H
X
L
External L to H NOP/WRITE ABORT (Begin Burst) High-Z
2,3
X
X
X
H
X
H
X
L
Next
L to H
WRITE ABORT (Continue Burst)
High-Z
1,2,3,
10
X
X
X
X
X
X
X
H
Current L to H
INHIBIT CLOCK
-
4
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 7 of 19
State Diagram for NTD SRAM
Recommended operating conditions at 3.3V I/O
Recommended operating conditions at 2.5V I/O
Absolute maximum ratings
1
1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
V
DD
, V
DDQ
0.5
+4.6
V
Input voltage relative to GND (input pins)
V
IN
0.5
V
DD
+ 0.5
V
Input voltage relative to GND (I/O pins)
V
IN
0.5
V
DDQ
+ 0.5
V
Power dissipation
P
D
1.8
W
DC output current
I
OUT
50
mA
Storage temperature (plastic)
T
stg
65
+150
o
C
Temperature under bias (Junction)
T
bias
65 +150
o
C
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage for inputs
V
DD
3.135
3.3
3.465
V
Supply voltage for I/O
V
DDQ
3.135
3.3
3.465
V
Ground supply
Vss
0
0
0
V
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage for inputs
V
DD
3.135
3.3
3.465
V
Supply voltage for I/O
V
DDQ
2.375
2.5
2.625
V
Ground supply
Vss
0
0
0
V
Ds
el
Dsel
Read
Read
Burst
Burst
Write
Read
Write
Burst
Read
Read
W
r
ite
Dsel
Read
Burst
Write
Dsel
Dse
l
Wri
te
W
rite
Burst
Dsel
Burst
Burst
Write
Read
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 8 of 19
DC electrical characteristics for 3.3V I/O operation
DC electrical characteristics for 2.5V I/O operation
*
V
IH
max < VDD +1.5V for pulse width less than 0.2 X t
CYC
**
V
IL
min = -1.5 for pulse width less than 0.2 X t
CYC
I
DD
operating conditions and maximum limits
Parameter
Sym
Conditions
Min
Max
Unit
Input leakage current
1
1 LBO, and ZZ pins have an internal pull-up or pull-down, and input leakage = 10
A.
|I
LI
|
V
DD
= Max, 0V < V
IN
< V
DD
-2
2
A
Output leakage current
|I
LO
|
OE
V
IH
, V
DD
= Max, 0V < V
OUT
< V
DDQ
-2
2
A
Input high (logic 1) voltage
V
IH
Address and control pins
2
*
V
DD
+0.3
V
I/O pins
2
*
V
DDQ
+0.3
Input low (logic 0) voltage
V
IL
Address and control pins
-0.3
**
0.8
V
I/O pins
-0.5
**
0.8
Output high voltage
V
OH
I
OH
= 4 mA, V
DDQ
= 3.135V
2.4
V
Output low voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 3.465V
0.4
V
Parameter
Sym
Conditions
Min
Max
Unit
Input leakage current
|I
LI
|
V
DD
= Max, 0V < V
IN
< V
DD
-2
2
A
Output leakage current
|I
LO
|
OE
V
IH
, V
DD
= Max, 0V < V
OUT
< V
DDQ
-2
2
A
Input high (logic 1) voltage
V
IH
Address and control pins
1.7
*
V
DD
+0.3
V
I/O pins
1.7
*
V
DDQ
+0.3
V
Input low (logic 0) voltage
V
IL
Address and control pins
-0.3
**
0.7
V
I/O pins
-0.3
**
0.7
V
Output high voltage
V
OH
I
OH
= 4 mA, V
DDQ
= 2.375V
1.7
V
Output low voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 2.625V
0.7
V
Parameter
Sym
Test conditions
-166
-133
Unit
Operating power supply
current
1
1
I
CC
given with no output loading. I
CC
increases with faster cycle times and greater output loading.
I
CC
CE0 < V
IL
, CE1 > V
IH
, CE2 < V
IL
, f = f
Max
,
I
OUT
= 0 mA, ZZ
< V
IL
475
400
mA
Standby power supply current
I
SB
All V
IN
0.2V or > V
DD
0.2V, Deselected,
f = f
Max
, ZZ
< V
IL
130
100
mA
I
SB1
Deselected, f = 0, ZZ
< 0.2V,
all V
IN
0.2V or V
DD
0.2V
30
30
I
SB2
Deselected, f = f
Max
, ZZ
V
DD
0.2V,
all V
IN
V
IL
or
V
IH
30
30
AS7C33256NTD32A
AS7C33256NTD36A
11/30/04, v. 2.1
Alliance Semiconductor
P. 9 of 19
Timing characteristics for 3.3 V I/O operation
Parameter
Symbol
166
133
Unit
Notes
1
1 Refer to "notes" on page 16.
Min
Max
Min
Max
Clock frequency
f
Max
166
133
MHz
Cycle time
t
CYC
6
7.5
ns
Clock access time
t
CD
3.5
4.0
ns
Output enable low to data valid
t
OE
3.5
4.0
ns
Clock high to output low Z
t
LZC
0
0
ns
2,3,4
Data output invalid from clock high
t
OH
1.5
1.5
ns
2
Output enable low to output low Z
t
LZOE
0
0
ns
2,3,4
Output enable high to output High Z
t
HZOE
3.5
4.0
ns
2,3,4
Clock high to output High Z
t
HZC
3.5
4.0
ns
2,3,4
Output enable high to invalid output
t
OHOE
0
0
ns
Clock high pulse width
t
CH
2.4
2.5
ns
5
Clock low pulse width
t
CL
2.3
2.5
ns
5
Address and control setup to clock high
t
AS
1.5
1.5
ns
6
Data setup to clock high
t
DS
1.5
1.5
ns
6
Write setup to clock high
t
WS
1.5
1.5
ns
6,7
Chip select setup to clock high
t
CSS
1.5
1.5
ns
6,8
Address hold from clock high
t
AH
0.5
0.5
ns
6
Data hold from clock high
t
DH
0.5
0.5
ns
6
Write hold from clock high
t
WH
0.5
0.5
ns
6,7
Chip select hold from clock high
t
CSH
0.5
0.5
ns
6,8
Clock enable
setup to clock high
t
CENS
1.5
1.5
ns
6
Clock enable hold from clock high
t
CENH
0.5
0.5
ns
6
ADV/LD
setup to clock high
t
ADVS
1.5
1.5
ns
6
ADV/LD
hold from clock high
t
ADVH
0.5
0.5
ns
6
AS7C33256NTD32A
AS7C33256NTD36A
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Alliance Semiconductor
P. 10 of 19
Snooze Mode Electrical Characteristics
Timing characteristics for 2.5 V I/O operation
Parameter
Symbol
166
133
Unit
Notes
1
Min
Max
Min
Max
Clock frequency
f
Max
166
133
MHz
Cycle time
t
CYC
6
7.5
ns
Clock access time
t
CD
3.8
4.2
ns
Output enable low to data valid
t
OE
3.5
4.0
ns
Clock high to output low Z
t
LZC
0
0
ns
2,3,4
Data output invalid from clock high
t
OH
1.5
1.5
ns
2
Output enable low to output low Z
t
LZOE
0
0
ns
2,3,4
Output enable high to output High Z
t
HZOE
3.5
4.0
ns
2,3,4
Clock high to output High Z
t
HZC
3.5
4.0
ns
2,3,4
Output enable high to invalid output
t
OHOE
0
0
ns
Clock high pulse width
t
CH
2.4
2.5
ns
5
Clock low pulse width
t
CL
2.3
2.5
ns
5
Address setup to clock high
t
AS
1.7
1.7
ns
6
Data setup to clock high
t
DS
1.7
1.7
ns
6
Write setup to clock high
t
WS
1.7
1.7
ns
6,7
Chip select setup to clock high
t
CSS
1.7
1.7
ns
6,8
Address hold from clock high
t
AH
0.7
0.7
ns
6
Data hold from clock high
t
DH
0.7
0.7
ns
6
Write hold from clock high
t
WH
0.7
0.7
ns
6,7
Chip select hold from clock high
t
CSH
0.7
0.7
ns
6,8
Clock enable
setup to clock high
t
CENS
1.7
1.7
ns
6
Clock enable hold from clock high
t
CENH
0.7
0.7
ns
6
ADV/LD
setup to clock high
t
ADVS
1.7
1.7
ns
6
ADV/LD
hold from clock high
t
ADVH
0.7
0.7
ns
6
1 Refer to "notes" on page 16.
Description
Conditions
Symbol
Min
Max
Units
Current during Snooze Mode
ZZ > V
IH
I
SB2
30
mA
ZZ active to input ignored
t
PDS
2
cycle
ZZ inactive to input sampled
t
PUS
2
cycle
ZZ active to SNOOZE current
t
ZZI
2
cycle
ZZ inactive to exit SNOOZE current
t
RZZI
0
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Alliance Semiconductor
P. 11 of 19
Key to switching waveforms
Timing waveform of read cycle
Undefined
Falling input
Rising input
don't care
t
CH
t
CYC
t
CL
t
AS
CLK
CEN
R/W
t
CEH
A1
A2
A3
Address
t
AH
t
CES
t
WS
t
WH
CE0,CE2
t
ADVS
t
CSH
Dout
CE1
t
ADVH
t
OE
t
LZOE
t
HZOE
Q(A1)
Q(A2Y`01)
Q(A2)
Q(A3)
t
HLZC
OE
ADV/LD
BWn
t
WS
t
WH
Q(A2Y`10)
Q(A2Y`11)
Read
Q(A1)
DSEL
Read
Q(A2)
Continue
Read
Q(A2Y`01)
Continue
Read
Q(A2Y`10)
Continue
Read
Q(A2Y`11)
Inhibit
Clock
Read
Q(A3)
Continue
Read
Q(A3Y`01)
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Alliance Semiconductor
P. 12 of 19
Timing waveform of write cycle
t
CH
t
CYC
t
CL
t
AS
CLK
CEN
R/W
t
CEH
A1
A2
A3
Address
t
AH
t
CES
CE0,CE2
t
ADVS
t
CSH
Din
CE1
t
ADVH
t
HZOE
D(A1)
D(A2)
D(A3)
t
DS
OE
ADV/LD
t
DH
Q(n-2)
Dout
BWn
Q(n-1)
D(A2Y`01)
D(A2Y`10) D(A2Y`11)
Write
D(A1)
DSEL
Write
D(A2)
Continue
Write
D(A2Y`01)
Continue
Write
D(A2Y`10)
Continue
Write
D(A2Y`11)
Inhibit
Clock
Write
D(A3)
Continue
Write
D(A3Y`01)
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Alliance Semiconductor
P. 13 of 19
Timing waveform of read/write cycle
Note: = XOR when LBO = high/no connect. = ADD when LBO = low. BW[a:d] is don't care.
t
CH
t
CYC
t
CL
t
CENS
t
OH
t
OE
CLK
CEN
CE0, CE2
ADV/LD
R/W
ADDRESS
D/Q
OE
Command
t
HZOE
BWn
A2
A1
A3
A5
A4
A7
A6
D(A1)
D(A5)
Q(A6)
D(A2)
D(A201)
Q(A3)
Q(A4)
Q(A401)
t
CENH
t
DS
t
DH
t
LZC
t
CD
t
HZC
t
LZOE
Read
Q(A3)
Read
Q(A4)
Burst
Read
Q(A401)
Write
D(A5)
Read
Q(A6)
Write
D(A7)
DSEL
t
CSS
t
ADVH
t
WS
t
WH
t
WS
t
WH
CE1
Write
D(A1)
Write
D(A2)
t
ADVS
t
CSH
t
AS
t
AH
Burst
Write
D(A201)
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Alliance Semiconductor
P. 14 of 19
NOP, stall and deselect cycles
Note: = XOR when LBO = high/no connect; = ADD when LBO = low. OE is low.
CLK
CEN
CE0, CE2
ADV/LD
R/W
Address
D/Q
Command
BWn
A1
A2
Q(A1)
D(A2)
Q(A101)
Q(A110)
Burst
Q(A101)
STALL
DSEL
Burst
DSEL
Write
D(A2)
Burst
NOP
D(A201)
Write
NOP
D(A3)
A3
Read
Q(A1)
Burst
Q(A110)
Burst
D(A210)
CE1
AS7C33256NTD32A
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11/30/04, v. 2.1
Alliance Semiconductor
P. 15 of 19
Timing waveform of snooze mode
AC test conditions
CLK
All inputs
ZZ
t
ZZI
I
supply
(except ZZ)
Dout
t
PUS
ZZ recovery cycle
I
SB2
t
RZZI
ZZ setup cycle
Deselect or Read Only
Deselect or Read Only
Normal
operation
Cycle
High-Z
Z
0
=50
D
out
50
V
L
=1.5V
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Output Load: see Figure B,
except for
t
LZC
, t
LZOE
, t
HZOE
, t
HZC
see Figure C.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
353
/1538
5 pF*
319
/1667
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
AS7C33256NTD32A
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11/30/04, v. 2.1
Alliance Semiconductor
P. 16 of 19
Notes
1
For test conditions, see AC Test Conditions, Figures A, B, C.
2
This parameter measured with output load condition in Figure C
3
This parameter is sampled and not 100% tested.
4
t
HZOE
is less than t
LZOE
; and t
HZC
is less than t
LZC
at any given temper-
ature and voltage.
5
t
HZCN
is a
`no load' parameter to indicate exactly when SRAM outputs
have stopped driving.
6
I
CC
given with no output loading. I
CC
increases with faster cycle times
and greater output loading.
7
Transitions are measured 500 mV from steady state voltage. Output
loading specified with C
L
= 5 pF as in Figure C.
8
t
CH
measured as high above VIH, and t
CL
measured as low below VIL
9
This is a synchronous device. All addresses must meet the specified
setup and hold times for all rising edges of CLK. All other synchronous
inputs must meet the setup and hold times with stable logic levels for all
rising edges of CLK when chip is enabled.
AS7C33256NTD32A
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11/30/04, v. 2.1
Alliance Semiconductor
P. 17 of 19
Package Dimensions
He E
Hd
D
b
e
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.80
14.20
E
19.80
20.20
e
0.65 nominal
Hd
15.80
16.20
He
21.80
22.20
L
0.45
0.75
L1
1.00 nominal
0
7
Dimensions in millimeters
100-pin quad flat pack (TQFP)
A1
A2
L1
L
c
AS7C33256NTD32A
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11/30/04, v. 2.1
Alliance Semiconductor
P. 18 of 19
O
rdering information
Note: Add suffix `N' to he above part numbers for Lead Free Parts (Ex. AS7C33256NTD32A-166TQCN)
Part numbering guide
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33 = 3.3V
3.Organization:
256 = 256K
4.NTD
TM
= No Turn-around Delay. Pipelined mode.
5.Organization: 32 = x32; 36 = x36
6.Production version: A = first production version
7.Clock speed (MHz)
8.Package type: TQ = TQFP.
9.Operating temperature: C = commercial (
0
C to 70 C); I = industrial (-40 C to 85 C)
10. N = Lead free part
Package
Width
166 MHz
133 MHz
TQFP
32
AS7C33256NTD32A
-166TQC
AS7C33256NTD32A
-133TQC
TQFP
32
AS7C33256NTD32A
-166TQI
AS7C33256NTD32A
-133TQI
TQFP
36
AS7C33256NTD36A
-166TQC
AS7C33256NTD36A
-133TQC
TQFP
36
AS7C33256NTD36A
-166TQI
AS7C33256NTD36A
-133TQI
AS7C
33
256
NTD
32/36
A
XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
AS7C33256NTD32A
AS7C33256NTD36A
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Part Number:AS7C33256NTD36A
Document Version: v. 2.1
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