December 2002
Copyright Alliance Semiconductor. All rights reserved.
AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 1 of 10
9 . 65$0 ZLWK 17'
TM
Features
Organization: 262,144 words 16 or 18 bits
NTD
TM1
architecture for efficient bus operation
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/4.0/5.0 ns
Fast OE access time: 3.5/4.0/5.0 ns
Fully synchronous operation
Flow-through or pipelined mode
Asynchronous output enable control
1 NTD is a trademark of Alliance Semiconductor Corporation.
Economical 100-pin TQFP package
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
W
r
ite Bu
ff
er
Address
D
Q
CLK
register
Output
Register
DQ [a:b]
16/18
16/18
18
18
CLK
CE0
CE1
CE2
A[17:0]
OE
CLK
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
16/18
16/18
16/18
OE
256K x 16/18
SRAM
Array
R/W
DQ [a:b]
BWa
BWb
CLK
Q
D
FT
ADV / LD
LBO
Burst logic
addr. registers
Write delay
16/18
18
ZZ
CLK
Logic block diagram
Pin arrangement for TQFP (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0 CE1 NC NC BW
b
BW
a
CE2 V
DD
V
SS
CLK
R/
W
CEN OE ADV
/
L
D
NC NC A A
TQFP 14x20mm
A16
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQB
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A17
NC
NC
V
DDQ
V
SSQ
NC
DQPa, NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
V
DD
DQPb,
Selection Guide
-166
-133
-100
Units
Minimum cycle time
6
7.5
10
ns
Maximum pipelined clock frequency
166
133
100
MHz
Maximum pipelined clock access time
3.5
4
5
ns
Maximum operating current
475
425
325
mA
Maximum standby current
130
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
mA
Note: Pins 24, 74 are NC for 16
AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C33256NTD16A/18A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) organized as
262,144 words 16 or 18 bits and incorporates a LATE LATE Write.
This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD) architecture, featuring an enhanced Write operation that
improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to
the device on the same clock edge. If a Read command follows this Write command, the system must wait for two 'dead' cycles for valid data
to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or Read-Modify-
Write operations.
NTD devices use the memory bus more efficiently by introducing a write latency that matches the two-cycle pipelined or one-cycle flow-
through read latency. Write data is applied two cycles after the Write command and address, allowing the Read pipeline to clear. With NTD,
Write and Read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform Write cycles. Byte Write enable controls write access to specific bytes, or it can be tied low for full 16/18 bit
writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two
clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations. It can be tied low for
normal operations. Outputs go to a high impedance state when the device is deselected by any of the three chip enable inputs. In pipelined
mode, a two-cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write, and deselect operations. When ADV is high, external addresses, chip select, and R/W
pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including
burst, can be stalled using the clock enable input CEN=1.
The AS7C33256NTD18A and AS7C33256NTD16A operate with a 3.3V 5% power supply for the device core (V
DD
). DQ circuits use a
separate power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 1420 mm TQFP package.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
Address and control pins
V
in
= 0V
5
pF
I/O capacitance
C
I/O
I/O pins
V
in
= V
out
= 0V
7
pF
Burst order
Interleaved burst order
LBO = 1
Linear burst order
LBO = 0
Starting address
00
01
10
11
Starting address
00
01
10
11
First increment
01
00
11
10
First increment
01
00
11
10
Second increment
10
11
00
01
Second increment
10
11
00
01
Third increment
11
10
01
10
Third increment
11
10
01
10
AS7C33256NTD16A
AS7C33256NTD18A
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Alliance Semiconductor
P. 3 of 10
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Signal descriptions
Signal
I/O
Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
CEN
I
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1
I
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is high.
ADV/LD
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new address
is loaded.
R/W
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
BW[a,b]
I
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
I
STATIC
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This input should be static when the
device is in operation.
FT
I
STATIC
Flow-through mode. When low, enables single register flow-through mode. Connect to V
DD
if unused or for pipelined operation.
ZZ
I
ASYNC
Snooze. Places device in low power mode. Data is retained. Connect to GND if unused.
NC
-
-
No connects. Note that pin 83 and 84 will be used for future address expansion to 8Mb and
16Mb density.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
V
DD
, V
DDQ
0.5
+4.6
V
Input voltage relative to GND (input pins)
V
IN
0.5
V
DD
+ 0.5
V
Input voltage relative to GND (I/O pins)
V
IN
0.5
V
DDQ
+ 0.5
V
Power dissipation
P
D
1.8
W
DC output current
I
OUT
50
mA
Storage temperature (plastic)
T
stg
65
+150
o
C
Temperature under bias (Junction)
T
bias
65 +135
o
C
AS7C33256NTD16A
AS7C33256NTD18A
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Alliance Semiconductor
P. 4 of 10
Key
:
X = don't care. L = low. H = high.
1. Should be low for Burst write, unless a specific byte needs to be inhibited
2. Refer to state diagram below.
State Diagram for NTD SRAM
Synchronous truth table
CE0
CE1
CE2
ADV/LD R/W BW[a,b]
OE
CEN
Address source
CLK
Operation
H
X
X
L
X
X
X
L
NA
L to H
Deselect, high-Z
X
L
X
L
X
X
X
L
NA
L to H
Deselect, high-Z
X
X
H
L
X
X
X
L
NA
L to H
Deselect, high-Z
L
H
L
L
H
X
X
L
External
L to H
Begin read
L
H
L
L
L
L
X
L
External
L to H
Begin write
X
X
X
H
X
X
1
X
L
Burst counter
L to H
Burst
2
X
X
X
X
X
X
X
H
Stall
L to H
Inhibit the CLK
TQFP thermal resistance
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(Junction to Ambient)
1
1
This parameter is sampled.
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
1-layer
JA
40
C/W
4-layer
JA
22
C/W
Thermal resistance
(Junction to Top of Case)
1
JC
8
C/W
Dsel
Dsel
Read
Read
Burst
Burst
Write
Read
Write
Burst
Read
Read
Wr
i
t
e
Dsel
Rea
d
Burst
Write
Dsel
Dse
l
Wr
ite
W
rit
e
Burst
Dsel
Burst
Burst
Write
Read
AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 5 of 10
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
DD
3.135
3.3
3.465
V
GND
0.0
0.0
0.0
V
3.3V I/O supply
voltage
V
DDQ
3.135
3.3
3.465
V
GND
Q
0.0
0.0
0.0
2.5V I/O supply
voltage
V
DDQ
2.35
2.5
2.65
V
GND
Q
0.0
0.0
0.0
Input voltages
1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V operation, contact factory for input specifications.
Address and
control pins
V
IH
2.0
V
DD
+ 0.3
V
V
IL
0.5
2
2 V
IL
min = 2.0V for pulse width less than 0.2 x t
RC
.
0.8
V
I/O pins
V
IH
2.0
V
DDQ
+ 0.3
V
V
IL
-0.5
2
0.8
Ambient operating temperature
T
A
0
70
C
DC electrical characteristics for 3.3V I/O operation
Parameter
Symbol Test conditions
166
133
100
Unit
Min
Max
Min
Max
Min
Max
Input leakage current
|
I
LI
|
1
1 LBO pin has an internal pull-up, and input leakage = 10
A.
V
DD
= Max, V
in
= GND to V
DD
2
2
2
A
Output leakage
current
|
I
LO
|
OE
V
IH,
V
DD
= Max,
V
out
= GND to V
DD
2
2
2
A
Operating power
supply current
I
CC
2
2 I
CC
given with no output loading. I
CC
increases with faster cycle times and greater output loading
CE = V
IL
, CE = V
IH
, CE = V
IL
,
f = f
max,
I
out
= 0 mA
450
425
325
mA
Standby power supply
current
I
SB
'HVHOHFWHG
f = f
max
110
100
90
mA
I
SB1
'HVHOHFWHG
f = 0
DOO 9IN
0.2V or
V
DD
- 0.2V
30
30
30
mA
I
SB2
Deselected, f=f
Max
, ZZ
V
DD
-
0.2V
All V
IN
V
IL
or
V
IH
30
30
30
mA
Output voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 3.6V
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
DDQ
= 3.0V
2.4
2.4
2.4
V
DC electrical characteristics for 2.5V I/O operation
Parameter
Symbol Test conditions
166
133
100
Unit
Min
Max
Min
Max
Min
Max
Output leakage
current
|
I
LO
|
OE
V
IH,
V
DD
= Max,
V
out
= GND to V
DD
-1
1
-1
1
-1
1
A
Output voltage
V
OL
I
OL
= 2 mA, V
DDQ
= 2.65V
0.7
0.7
0.7
V
V
OH
I
OH
= 2 mA, V
DDQ
= 2.35V
1.7
1.7
1.7
AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 6 of 10
Timing characteristics over operating range
Parameter
Symbol
166
133
100
Unit
Notes
1
1 See "Notes" on page 9
Min
Max
Min
Max
Min
Max
Clock frequency
F
MAX
-
166
-
133
-
100
MHz
Cycle time (pipelined mode)
t
CYC
6
-
7.5
-
10
-
ns
Cycle time (flow-through mode)
t
CYCF
10
-
12
-
12
-
ns
Clock access time (pipelined mode)
t
CD
-
3.5
-
4.0
-
5.0
ns
Clock access time (flow-through
mode)
t
CDF
-
9
-
10
-
12
ns
Output enable low to data valid
t
OE
-
3.5
-
4.0
-
5.0
ns
Clock high to output low Z
t
LZC
0
-
0
-
0
-
ns
2,3,4
Data output invalid from clock high
t
OH
1.5
-
1.5
-
1.5
-
ns
4
Output enable low to output low Z
t
LZOE
0
-
0
-
0
-
ns
2,3,4
Output enable high to output high Z
t
HZOE
-
3.5
-
4.0
-
4.5
ns
2,3,4
Clock high to output high Z
t
HZC
-
3.5
-
4.0
-
4.5
ns
2,3,4
Clock high to output high Z
t
HZCN
-
1.5
-
2.0
-
2.5
ns
5
Clock high pulse width
t
CH
2.4
-
2.5
-
3.0
-
ns
6,7
Clock low pulse width
t
CL
2.2
-
2.5
-
3.0
-
ns
6
Address setup to clock high
t
AS
1.5
-
1.5
-
1.5
-
ns
7
Data setup to clock high
t
DS
1.5
-
1.5
-
1.5
-
ns
7
Write setup to clock high
t
WS
1.5
-
1.5
-
1.5
-
ns
7
Chip select setup to clock high
t
CSS
1.5
-
1.5
-
1.5
-
ns
7
Clock enable setup to clock high
t
CENS
1.5
-
1.5
-
1.5
-
ns
7
ADV setup to clock high
t
ADVS
1.5
-
1.5
-
1.5
-
ns
7
Address hold from clock high
t
AH
0.5
-
0.5
-
0.5
-
ns
7
Data hold from clock high
t
DH
0.5
-
0.5
-
0.5
-
ns
7
Write hold from clock high
t
WH
0.5
-
0.5
-
0.5
-
ns
7
Chip select hold from clock high
t
CSH
0.5
-
0.5
-
0.5
-
ns
7
Clock enable hold from clock high
t
CENH
0.5
-
0.5
-
0.5
-
ns
7
ADV hold from clock high
t
ADVH
0.5
-
0.5
-
0.5
-
ns
7
AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 7 of 10
Timing waveform of read/write cycle
Note: = XOR when LBO = high/no connect. = ADD when LBO = low.
BW[a:b] is don't care.
Undefined output/don't care
Key to waveform
W
&+
W
&<&
W
&/
W
&(16
W
2+
W
2(
&/.
&(1
&( &(
$'9/'
5:
$''5(66
'4
2(
&RPPDQG
W
+=2(
%:Q
$
$
$
$
$
$
$
'$
'$
4$
'$
'$
4$
4$
4$
W
&(1+
W
'6
W
'+
W
/=&
W
&'
W
+=&
W
/=2(
BURST
WRITE
D(A2
01)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4
01)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DSEL
WRITE
D(A1)
WRITE
D(A2)
W
&66
W
$'9+
W
:6
W
:+
W
:6
W
:+
t
&6+
t
AS
t
AH
'4
'$
'$
4$
'$
'$
4$
4$
4$
SLSHOLQHG
IORZWKURXJK
&(
W
$'96
'$7
AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 8 of 10
NOP, stall and deselect cycles
Note: OE is low.
&/.
&(1
&( &(
$'9/'
5:
$''5(66
'4
&RPPDQG
%:Q
$
$
4$
'$
4$
4$
BURST
Q(A1
0
1)
STALL
DSEL
BURST
DSEL
WRITE
D(A2)
BURST
NOP
D(A2
01)
WRITE
NOP
D(A3)
$
'4
4$
'$
4$
4$
READ
Q(A1)
BURST
Q(A1
10)
BURST
D(A2
10)
&(
SLSHOLQHG
IORZWKRXJK
'$
AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 9 of 10
AC test conditions
Z
0
=50
D
out
50
V
L
=1.5V
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Output Load: For t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C. For all others, see Figure B.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
353
/ 1538
5 pF*
319
/ 1667
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O,
+2.5V for 2.5V I/O
Notes:
Package dimensions: 100-pin quad flat pack (TQFP)
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
0.65 nominal
Hd
15.90
16.10
He
21.90
22.10
L
0.45
0.75
L1
1.00 nominal
a
0
7
Dimensions in millimeters
He
E
Hd
D
b
e
A1 A2
L1
L
c
1
For test conditions, see AC Test Conditions, Figures A, B, and C.
2
This parameter measured with output load condition in Figure C
3
This parameter is sampled and not 100% tested.
4
t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given tempera-
ture and voltage.
5
t
HZCN
is a
no-load parameter to indicate exactly when SRAM outputs
have stopped driving.
6
t
CH
measured as high above VIH, and t
CL
measured as low below VIL
7
This is a synchronous device. All addresses must meet the specified setup
and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times with stable logic levels for all rising
edges of CLK when chip is enabled.
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AS7C33256NTD16A
AS7C33256NTD18A
12/2/02,
v.1.7
Alliance Semiconductor
P. 10 of 10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33 = 3.3V
3.Organization: 256 = 256K
4.
NTD
= No Turnaround Delay
5.Organization: 16 = x16, 18 = x18
6.Production version: A = first production version
7.Clock speed (MHz)
8.Package type: TQ = TQFP
9.Operating temperature: C = commercial (
0
C to 70
C). I = industrial (
-40
C to 85
C)
Ordering information
Package
Width
166 MHz
133 MHz
100 MHz
TQFP
16
AS7C33256NTD16A-166TQC
AS7C33256NTD16A-133TQC
AS7C33256NTD16A-100TQC
TQFP
16
AS7C33256NTD16A-166TQI
AS7C33256NTD16A-133TQI
AS7C33256NTD16A-100TQI
TQFP
18
AS7C33256NTD18A-166TQC
AS7C33256NTD18A-133TQC
AS7C33256NTD18A-100TQC
TQFP
18
AS7C33256NTD18A-166TQI
AS7C33256NTD18A-133TQI
AS7C33256NTD18A-100TQI
Part numbering guide
AS7C
33
256
NTD
16/18
A
XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
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ZIP