March 2003
Advance Information
Copyright Alliance Semiconductor. All rights reserved.
AS7C331MPFS18A
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Alliance Semiconductor
1 of 21
1M x 18 pipelined burst synchronous SRAM
Features
Organization: 1,048,576 x18 bits
Fast clock speeds to 200MHz in LVTTL/LVCMOS
Fast clock to data access: 3/3.4/3.8 ns
Fast OE access time: 3/3.4/3.8 ns
Fully synchronous register-to-register operation
Single register flow-through mode
Single-cycle deselect
Asynchronous output enable control
Available 100-pin TQFP and 165-ball BGA packages
Byte write enables
Multiple chip enables for easy expansion
3.3 V core power supply
2.5 V or 3.3V I/O operation with separate V
DDQ
NTDTM pipelined architecture available (AS7C331MNTD18A,
AS7C33512NTD32A/ AS7C33512NTD36A)
Logic block diagram
Selection guide
-200
-166
-133
Units
Minimum cycle time
5
6
7.5
ns
Maximum clock frequency
200
166
133
MHz
Maximum pipelined clock access time
3.0
3.4
3.8
ns
Maximum operating current
370
340
320
mA
Maximum standby current
130
120
110
mA
Maximum CMOS standby current (DC)
70
70
70
mA
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
20
18
20
A[19:0]
20
Address
D
Q
CS
CLK
register
1M
[
18
Memory
array
18
18
DQb
CLK
D
Q
Byte Write
registers
DQa
CLK
D
Q
Byte Write
registers
Enable
CLK
D
Q
register
Enable
CLK
D
Q
delay
register
CE
Output
registers
Input
registers
Power
down
DQ[a,b]
2
CE0
CE1
CE2
BW
b
BW
a
OE
ZZ
OE
FT
CLK
CLK
BWE
GWE
18
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AS7C331MPFS18A
Pin and ball designations
Pin configuration for 100-pin TQFP
Ball assignments for 165-ball BGA
$
NC
A
CE0
BWb
NC
CE2
BWE
ADSC
ADV
A
A
%
NC
A
CE1
NC
BWa
CLK
GWE
OE
ADSP
A
NC
&
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPa
'
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
(
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
)
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
*
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
+
FT
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
-
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
.
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
/
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
0
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
1
DQPb
NC
VDDQ
VSS
NC
A
NC
VSS
VDDQ
NC
NC
3
NC
NC
A
A
TDI
A1
1
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
TDO
A
A
A
A
5
LBO
NC
A
A
TMS
A0
1
TCK
A
A
A
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQPb
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQa
DQa
DQa
V
SSQ
V
DDQ
DQ
a
DQ
a
V
SS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BW
a
CE2
V
DD
V
SS
CLK
GW
E
BWE
OE
AD
SC
AD
SP
AD
V
A
A
NC
VDD
A
TQFP 14 20 mm
1M x 18
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3 of 21
AS7C331MPFS18A
Functional description
The AS7C331MPFS18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as
1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.
Fast cycle times of 5/6/7.5 ns with clock access times (t
CD
) of 3/3.4/3.8 ns enable 200, 166, and 133 MHz bus frequencies. Three chip
enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or
the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven on
the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes
are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count
sequence. With LBO driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally
to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip enable
CE0 blocks ADSP, but not ADSC.
The AS7C331MPFS18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
Address and control pins
V
IN
= 0V
5
pF
I/O capacitance
C
I/O
I/O pins
V
IN
= V
OUT
7
pF
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AS7C331MPFS18A
Signal descriptions
Write enable truth table (per byte)
.H\ X = don't care; L = low; H = high; B
WE, BWn
= internal write signal
Signal
I/O
Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock.
A0A17
I
SYNC
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and when OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the "Synchronous truth table" for more information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active high and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe processor. Asserted low to load a new bus address or to enter standby
mode.
ADSC
I
SYNC
Address strobe controller. Asserted low to load a new address or to enter standby mode.
ADV
I
SYNC
Advance. Asserted low to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and
BW[a,b] control write enable.
BWE
I
SYNC
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE is high and BWE is
low. If any of BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If
all BW[AB] are inactive, the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO
I
STATIC
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This signal is internally pulled high.
18
TDO
O
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
TDI
I
SYNC
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
TMS
I
SYNC
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK
(BGA only).
TCK
O
SYNC
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
FT
I
STATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to
V
DD
if unused or for pipelined operation.
ZZ
I
ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Function
GWE
BWE
BWa
BWb
Write all bytes (a, b)
L
X
X
X
H
L
L
L
Write byte a
H
L
L
H
Write byte b
H
L
H
L
Read
H
H
X
X
H
L
H
H
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AS7C331MPFS18A
Synchronous truth table
Key: X = don't care, L = low, H = high
TQFP and BGA thermal resistance
CE0
CE1
CE2
ADSP
ADSC
ADV
BWn
1
1
See "Write enable truth table" on page 4 for more information.
OE
Address accessed
CLK
Operation
DQ
H
X
X
X
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
L
X
L
X
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
L
X
H
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
X
H
L
X
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
X
H
H
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
H
L
L
X
X
X
L
External
L to H
Begin read
Hi
-
Z
2
2 Q in flow-through mode.
L
H
L
L
X
X
X
H
External
L to H
Begin read
Hi
-
Z
L
H
L
H
L
X
F
L
External
L to H
Begin read
Hi
-
Z
2
L
H
L
H
L
X
F
H
External
L to H
Begin read
Hi
-
Z
X
X
X
H
H
L
F
L
Next
L to H
Continue read
Q
X
X
X
H
H
L
F
H
Next
L to H
Continue read
Hi
-
Z
X
X
X
H
H
H
F
L
Current
L to H
Suspend read
Q
X
X
X
H
H
H
F
H
Current
L to H
Suspend read
Hi
-
Z
H
X
X
X
H
L
F
L
Next
L to H
Continue read
Q
H
X
X
X
H
L
F
H
Next
L to H
Continue read
Hi
-
Z
H
X
X
X
H
H
F
L
Current
L to H
Suspend read
Q
H
X
X
X
H
H
F
H
Current
L to H
Suspend read
Hi
-
Z
L
H
L
H
L
X
T
X
External
L to H
Begin write
D
3
3
For a write operation following a read operation,
OE
must be high before the input data set up time and must be held high throughout the input hold time
X
X
X
H
H
L
T
X
Next
L to H
Continue write
D
H
X
X
X
H
L
T
X
Next
L to H
Continue write
D
X
X
X
H
H
H
T
X
Current
L to H
Suspend write
D
H
X
X
X
H
H
T
X
Current
L to H
Suspend write
D
Description
Symbol
Typical
Units
Conditions
Thermal resistance
(junction to ambient)
1
1
This parameter is sampled.
1 layer
JA
40
C/W
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
4 layer
JA
22
C/W
Thermal resistance
(junction to top of case)
1
JC
8
C/W
AS7C331MPFS18A
4/8/03, v. 032003 Advance Info
Alliance Semiconductor
6 of 21
Absolute maximum ratings
Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating con-
ditions may affect reliability.
Recommended operating conditions
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
V
DD
, V
DDQ
0.5
+4.6
V
Input voltage relative to GND (input pins)
V
IN
0.5
V
DD
+ 0.5
V
Input voltage relative to GND (I/O pins)
V
IN
0.5
V
DDQ
+ 0.5
V
Power dissipation
P
D
1.8
W
DC output current
I
OUT
20 mA
mA
Storage temperature (plastic)
T
stg
65
+150
o
C
Temperature under bias
T
bias
65 +135
o
C
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
DD
3.135
3.3
3.6
V
V
SS
0.0
0.0
0.0
3.3V I/O supply voltage
V
DDQ
3.135
3.3
3.6
V
V
SSQ
0.0
0.0
0.0
2.5V I/O supply voltage
V
DDQ
2.35
2.5
2.9
V
V
SSQ
0.0
0.0
0.0
Input voltages
1
1
Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
Address and
control pins
V
IH
2.0
V
DD
+ 0.3
V
V
IL
0.3
2
2 V
IL
min = 2.0V for pulse width less than 0.2 t
RC
.
0.8
I/O pins
V
IH
2.0
V
DDQ
+ 0.3
V
V
IL
0.5
0.8
Ambient operating temperature
T
A
0
70
C
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7 of 21
AS7C331MPFS18A
DC electrical characteristics for 3.3V I/O operation
DC electrical characteristics for 2.5V I/O operation
Parameter
Sym
Test conditions
200
166
133
Unit
Min Max Min Max Min Max
Input leakage
current
1
1 LBO, FTX, and ZZX pins and the 165 BGA JTAG pins (TMSX, TDIX, and TCKX) have an internal pull-up, and input leakage = 10
a.
|I
LI
|
V
DD
= Max, V
IN
= GND to V
DD
-2
2
-2
2
-2
2
A
Output leakage
current
|I
LO
|
OE
V
IH
, V
DD
= Max,
V
OUT
= GND to V
DD
-2
2
-2
2
-2
2
A
Operating power
supply current
2
2 I
CC
given with no output loading. I
CC
increases with faster cycle times and greater output loading.
I
CC
(Pipelined)
CE0 = V
IL
, CE1 = V
IH
, CE2 = V
IL
,
f = f
Max
, I
OUT
= 0 mA
370
340
320
mA
Operating power
supply current
2
I
CC
(Flow-through)
200
175
165
mA
Standby power
supply current
I
SB
Deselected, f = f
Max
, ZZ
V
IL
130
120
110
mA
I
SB1
Deselected, f = 0, ZZ
0.2V
all V
IN
0.2V or
V
DD
0.2V
70
70
70
I
SB2
Deselected, f = f
Max
, ZZ
V
DD
0.2V
All V
IN
V
IL
or
V
IH
60
60
60
Output voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 3.465V
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
DDQ
= 3.135V
2.4
2.4
2.4
Parameter
Sym
Test conditions
200
166
133
Unit
Min
Max
Min
Max
Min
Max
Output leakage
current
|I
LO
|
OE
V
IH
, V
DD
= Max,
V
OUT
= GND to V
DD
1
1
1
1
1
1
A
Output voltage
V
OL
I
OL
= 2 mA, V
DDQ
= 2.65V
0.7
0.7
0.7
V
V
OH
I
OH
= 2 mA, V
DDQ
= 2.35V
1.7
1.7
1.7
AS7C331MPFS18A
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Timing characteristics over operating range
Parameter
Sym
200
166
133
Unit
Notes
1
1
See "Notes" on page 19.
Min
Max
Min
Max
Min
Max
Clock frequency
f
Max
200
166
133
MHz
Cycle time (pipelined mode)
t
CYC
5
6
7.5
ns
Cycle time (flow-through mode)
t
CYCF
7.5
8.5
12
ns
Clock access time (pipelined mode)
t
CD
3.0
3.4
3.8
ns
Clock access time (flow-through mode)
t
CDF
7.5
8.5
10
ns
Output enable low to data valid
t
OE
3.0
3.4
3.8
ns
Clock high to output low Z
t
LZC
0
0
0
ns
2, 3, 4
Data output invalid from clock high
t
OH
1.5
1.5
1.5
ns
2
Output enable low to output low Z
t
LZOE
0
0
0
ns
2, 3, 4
Output enable high to output high Z
t
HZOE
3.0
3.4
3.8
ns
2, 3, 4
Clock high to output high Z
t
HZC
3.0
3.4
3.8
ns
2, 3, 4
Output enable high to invalid output
t
OHOE
0
0
0
ns
Clock high pulse width
t
CH
1.8
2.1
2.4
ns
5
Clock low pulse width
t
CL
1.8
2.2
2.4
ns
5
Address setup to clock high
t
AS
1.4
1.5
1.5
ns
6
Data setup to clock high
t
DS
1.4
1.5
1.5
ns
6
Write setup to clock high
t
WS
1.4
1.5
1.5
ns
6, 7
Chip select setup to clock high
t
CSS
1.4
1.5
1.5
ns
6, 8
Address hold from clock high
t
AH
0.4
0.5
0.5
ns
6
Data hold from clock high
t
DH
0.4
0.5
0.5
ns
6
Write hold from clock high
t
WH
0.4
0.5
0.5
ns
6, 7
Chip select hold from clock high
t
CSH
0.4
0.5
0.5
ns
6, 8
ADV setup to clock high
t
ADVS
1.4
1.5
1.5
ns
6
ADSP setup to clock high
t
ADSPS
1.4
1.5
1.5
ns
6
ADSC setup to clock high
t
ADSCS
1.4
1.5
1.5
ns
6
ADV hold from clock high
t
ADVH
0.4
0.5
0.5
ns
6
ADSP hold from clock high
t
ADSPH
0.4
0.5
0.5
ns
6
ADSC hold from clock high
t
ADSCH
0.4
0.5
0.5
ns
6
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9 of 21
AS7C331MPFS18A
IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the
critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully
compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
Disabling the JTAG feature
If the JTAG function is not being implemented, its pins/balls can be left unconnected. At power-up, the device will come up in a reset state
which will not interfere with the operation of the device.
Test access port (TAP)
Test clock (TCK)
The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the
TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.
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TAP controller state diagram
TAP controller block diagram
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AS7C331MPFS18A
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Test data-in (TDI)
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between
TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see
the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to
the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram.)
Test data-out (TDO)
The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state
machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP
Controller State Diagram.)
Performing a TAP RESET
You can perform a RESET by forcing TMS high (V
DD
) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and can
be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP registers
Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is
output on the TDO pin/ball on the falling edge of TCK.
Instruction register
You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/
balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the
controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation
of the board-level series test data path.
Bypass register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit
register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The
bypass register is set low (Vss) when the BYPASS instruction is executed.
Boundary scan register
The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 72-bit-long
register and the x18 configuration has a 53-bit-long register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and SAMPLE Z
instructions can be used to capture the contents of the I/O ring.
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM
package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.
Identification (ID) register
The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded with
a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.
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AS7C331MPFS18A
TAP instruction set
Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of
these instructions are reserved and should not be used.
Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot
preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this
state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is shifted
in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP controller.
The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM
responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in
a high-Z state.
EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1.
IDCODE
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. The
IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between
the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller is in
a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of
data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a 1149.1 mandatory
instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore, is not fully 1149.1
compliant.
Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output
can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there
is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the
TAP controller's capture setup plus hold time (
t
CS plus
t
CH). The SRAM clock input might not be captured correctly if there is no way in a design
to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and ignore the
value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/
PRELOAD instruction will have the same effect as the Pause-DR command.
BYPASS
The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between
TDI and TDO.
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Reserved
Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.
TAP timing diagram
TAP AC electrical characteristics
For notes 1 and 2, +10
o
C < T
J
< +110
o
C and +2.4V < V
DD
< +2.6V.
Description
Symbol
Min
Max
Units
Clock
Clock cycle time
t
THTH
100
ns
Clock frequency
f
TF
10
MHz
Clock high time
t
THTL
40
ns
Clock low time
t
TLTH
40
ns
Output Times
TCK low to TDO unknown
t
TLOX
0
ns
TCK low to TDO valid
t
TLOV
20
ns
TDI valid to TCK high
t
DVTH
10
ns
TCK high to TDI invalid
t
THDX
10
ns
Setup Times
TMS setup
t
MVTH
10
ns
Capture setup
t
CS
1
1
t
CS and
t
CH refer to the setup and hold time requirements of latching data
from the boundary scan register.
2
Test conditions are specified using the load in the figure TAP AC output
load equivalent.
10
ns
Hold Times
TMS hold
t
THMX
10
ns
Capture hold
t
CH
1
10
ns
W
7+7/
W
7/7+
W
7+7+
W
097+
W
7+0;
W
'97+
W
7+';
W
7/2;
W
7/29
7HVW &ORFN
7&.
7HVW 0RGH 6HOHFW
706
7HVW 'DWD,Q
7',
7HVW 'DWD2XW
7'2
'RQW FDUH
8QGHILQHG
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AS7C331MPFS18A
3.3V V
DD
, TAP DC electrical characteristics and operating conditions
(+10
o
C < T
J
< +110
o
C and +3.135V < V
DD
< +3.465V unless otherwise noted)
2.5V V
DD
, TAP DC electrical characteristics and operating conditions
(+10
o
C < T
J
< +110
o
C and +2.4V < V
DD
< +2.6V unless otherwise noted)
1. All voltage referenced to V
SS
(GND).
2. Overshoot: V
IH
(AC)
V
DD
+ 1.5V for t
t
KHKH/2
Undershoot: V
IL
(AC)
-0.5 for t
t
KHKH/2
Power-up: V
IH
+2.6V and V
DD
2.4V and V
DDQ
1.4V for t
200ms
During normal operation, V
DDQ
must not exceed V
DD
. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than t
KHKL
(Min) or oper-
ate at frequencies exceeding f
KF
(Max).
Description
Conditions
Symbol
Min
Max
Units
Notes
Input high (logic 1) voltage
V
IH
2.0
V
DD
+ 0.3
V
1, 2
Input low (logic 0) voltage
V
IL
-0.3
0.8
V
1, 2
Input leakage current
0V
V
IN
V
DD
IL
I
-5.0
5.0
A
Output leakage current
Outputs disabled,
0V
V
IN
V
DDQ
(DQx)
IL
O
-5.0
5.0
A
Output low voltage
I
OLC
= 100
A
V
OL1
0.7
V
1
Output low voltage
I
OLT
= 2mA
V
OL2
0.8
V
1
Output high voltage
I
OHS
= -100
A
V
OH1
2.9
V
1
Output high voltage
I
OHT
= -2mA
V
OH2
2.0
V
1
Description
Conditions
Symbol
Min
Max
Units
Notes
Input high (logic 1) voltage
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input low (logic 0) voltage
V
IL
-0.3
0.7
V
1, 2
Input leakage current
0V
V
IN
V
DD
IL
I
-5.0
5.0
A
Output leakage current
Outputs disabled,
0V
V
IN
V
DDQ
(DQx)
IL
O
-5.0
5.0
A
Output low voltage
I
OLC
= 100
A
V
OL1
0.2
V
1
Output low voltage
I
OLT
= 2mA
V
OL2
0.7
V
1
Output high voltage
I
OHS
= -100
A
V
OH1
2.1
V
1
Output high voltage
I
OHT
= -2mA
V
OH2
1.7
V
1
Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing reference levels. . . . . . . . . . 1.25V
Output reference levels . . . . . . . . . . . . . . 1.25V
Test load termination supply voltage. . . . 1.25V
TAP AC test conditions
TAP AC output load equivalent
7'2
=
2
9
S)
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Identification register definitions
Scan register sizes
Instruction codes
Instruction field
1M x 18
Description
Revision number (31:28)
xxxx
Reserved for version number.
Device depth (27:23)
xxxxx
Defines the depth of 1Mb words.
Device width (22:18)
xxxxx
Defines the width of x18 bits.
Device ID (17:12)
xxxxxx
Reserved for future use.
JEDEC ID code (11:1)
00000110100 Allows unique identification of SRAM vendor.
ID register presence indicator (0)
1
Indicates the presence of an ID register.
Register name
Bit size
Instruction
3
Bypass
1
ID
32
Boundary scan
x18:53
x36:72
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high-Z state.
Reserved
011
Do not use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
Reserved
101
Do not use. This instruction is reserved for future use.
Reserved
110
Do not use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
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AS7C331MPFS18A
165-ball BGA boundary scan order (x18)
Bit #s
Signal Name
Ball ID
1
SA
11P
2
SA
6N
3
SA
8P
4
SA
8R
5
SA
9R
6
SA
9P
7
SA
10P
8
SA
10R
9
SA
11R
10
DQa
10M
11
DQa
10L
12
DQa
10K
13
DQa
10J
14
ZZ
11H
15
DQa
11G
16
DQa
11F
17
DQa
11E
18
DQa
11D
19
DQPa
11C
20
SA
11A
21
SA
10A
22
SA
10B
23
ADV
9A
24
ADSP
9B
25
ADSC
8A
26
OE
8B
27
BWE
7A
Bit #s
Signal Name
Ball ID
28
GWE
7B
29
CLK
6B
30
CE2
6A
31
BWa
5B
32
BWb
4A
33
CE1
3B
34
CE0
3A
35
SA
2A
36
SA
2B
37
DQb
2D
38
DQb
2E
39
DQb
2F
40
DQb
2G
41
FT
1H
42
DQb
1J
43
DQb
1K
44
DQb
1L
45
DQb
1M
46
DQPb
1N
47
LBO
1R
48
SA
3P
49
SA
3R
50
SA
4R
51
SA
4P
52
SA1
6P
53
SA0
6R
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Key to switching waveforms
Timing waveform of read cycle
Note: = XOR when LBO = high/no connect; = ADD when LBO = low.
BW[a:b] is don't care.
Undefined/don't care
Falling input
Rising input
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
D
OUT
t
CSS
t
CSH
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
Load new address
ADV inserts wait states
Q(A210)
Q(A211)
Q(A3)
Q(A2)
Q(A201)
Q(A301)
Q(A310)
Q(A1)
A2
A1
A3
CE1
(pipelined mode)
D
OUT
Q(A210)
Q(A211)
Q(A3)
Q(A201)
Q(A301)
Q(A310)
Q(A311)
Q(A1)
(flow-through mode)
t
HZC
t
OE
t
LZOE
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Burst
Read
Q(A 201)
Read
Q(A3)
DSEL
Burst
Read
Q(A 210)
Suspend
Read
Q(A 210)
Burst
Read
Q(A 211)
Burst
Read
Q(A 301)
Burst
Read
Q(A 310)
Burst
Read
Q(A 311)
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AS7C331MPFS18A
Timing waveform of write cycle
Note: = XOR when LBO = high/no connect; = ADD when LBO = low.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Data In
t
CSH
t
ADVH
D(A201)
D(A210)
D(A3)
D(A2)
D(A201)
D(A301)
D(A310)
D(A1)
D(A211)
ADV suspends burst
ADSC loads new address
A1
A2
A3
t
CH
CE1
BW[a:d]
Read Q(A1)
Suspend
Write
D(A1)
Read
Q(A2)
Suspend
Write
D(A 2)
ADV
Burst
Write
D(A 201)
Suspend
Write
D(A 201)
ADV
Burst
Write
Q(A 210)
Write
D(A 3)
Burst
Write
D(A 301)
ADV
Burst
Write
Q(A 211)
ADV
Burst
Write
D(A 310)
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Timing waveform of read/write cycle
Note: = XOR when LBO = high/no connect; = ADD when LBO = low.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
D
IN
D
OUT
t
LZC
t
ADVH
t
LZOE
t
OE
t
CD
Q(A1)
Q(A301)
D(A2)
Q(A3)
Q(A310)
Q(A311)
A1
A2
A3
CE1
t
HZOE
(pipelined mode)
D
OUT
Q(A1)
Q(A301)
Q(A310)
(flow-through mode)
t
CDF
Q(A311)
DSEL
Suspend
Read
Q(A1)
Read
Q(A1)
Suspend
Write
D(A 2)
ADV
Burst
Read
D(A 301)
Suspend
Read
Q(A 311)
ADV
Burst
Read
Q(A 310)
ADV
Burst
Read
Q(A 311)
Read
Q(A2)
Read
Q(A3)
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AS7C331MPFS18A
AC test conditions
Notes
1
For test conditions, see "AC Test Conditions", Figures A, B, and C.
2
This parameter is measured with output load condition in Figure C.
3
This parameter is sampled but not 100% tested.
4
t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given temperature and voltage.
5
t
CH
is measured as high above VIH, and t
CL
is measured as low below VIL.
6
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
7
Write refers to GWE, BWE, and BW[a,b]
.
8
Chip select refers to CE0, CE1, and CE2.
Z
0
= 50
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Output load: For t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C. For all others, see Figure B.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
V
L
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
353
/1538
5 pF*
319
/1667
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
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Package dimensions
100-pin TQFP (quad flat pack)
165-ball BGA (ball grid array)
He E
Hd
D
b
e
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
0.65 nominal
Hd
15.90
16.10
He
21.90
22.10
L
0.45
0.75
L1
1.00 nominal
0
7
Dimensions in millimeters
A1 A2
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Copyright Alliance Sem iconductor Corporation. All rights reserved. Our three-point logo, our nam e and Intelliwatt are tradem arks or registered tradem arks of Alliance. All other brand and
product nam es m ay be the tradem arks of their respective com panies. Alliance reserves the right to m ake changes to this docum ent and its products at any tim e without notice. Alliance assum es no
responsibility for any errors that m ay appear in this docum ent. The data contained herein represents Alliance's best data and/or estim ates at the tim e of issuance. Alliance reserves the right to
change or correct this data at any tim e, without notice. If the product described herein is under developm ent, significant changes to these specifications are possible. The inform ation in this
product data sheet is intended to be general descriptive inform ation for potential custom ers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
custom er. Alliance does not assum e any responsibility or liability arising out of the application or use of any product described herein, and disclaim s any express or im plied warranties related to
the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, m erchantability, or infringem ent of any intellectual property rights, except as
express agreed to in Alliance's Term s and Conditions of Sale (which are available from Alliance). All sales of Alliance products are m ade exclusively according to Alliance's Term s and
Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, m ask works rights, tradem arks, or any other intellectual property rights
of Alliance or third parties. Alliance does not authorize its products for use as critical com ponents in life-supporting systems where a m alfunction or failure m ay reasonably be expected to result
in significant injury to the user, and the inclusion of Alliance products in such life-supporting system s im plies that the m anufacturer assum es all risk of such use and agrees to indem nify Alliance
against all claim s arising from such use.
AS7C331MPFS18A
4/8/03, v. 032003 Advance Info
Alliance Semiconductor
21 of 21
Ordering information
Part numbering guide
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 1M
4. Pipelined/flow-through mode (each device works in both modes)
5. Deselect: S = single cycle deselect
6. Organization: 18 = x18
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP; B = BGA
10. Operating temperature: C = commercial (0
C to 70
C); I = industrial (-40
C to 85
C)
Package &
Width
200 MHz
166 MHz
133 MHz
TQFP x18
AS7C331MPFS18A-200TQC
AS7C331MPFS18A-166TQC
AS7C331MPFS18A-133TQC
AS7C331MPFS18A-200TQI
AS7C331MPFS18A-166TQI
AS7C331MPFS18A-133TQI
BGA x18
AS7C331MPFS18A-200BC
AS7C331MPFS18A-166BC
AS7C331MPFS18A-133BC
AS7C331MPFS18A-200BI
AS7C331MPFS18A-166BI
AS7C331MPFS18A-133BI
AS7C
33
1M
PF
S
18
A
XXX
TQ or B
C/I
1
2
3
4
5
6
7
8
9
10
PDF 
ZIP