March 2003
Advance Information

&RS\ULJKW $OOLDQFH 6HPLFRQGXFWRU $OO ULJKWV UHVHUYHG

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

9 0 [ 65$0 ZLWK 17'

Features

· Organization: 1,048,576 words × 18 bits
· NTD

TM1

architecture for efficient bus operation

· Fast clock speeds to 200 MHz in LVTTL/LVCMOS
· Fast clock to data access: 3/3.4/3.8 ns
· Fast OE access time: 3/3.4/3.8 ns
· Fully synchronous operation
· Flow-through or pipelined mode
· Asynchronous output enable control

1. NTD

is a trademark of Alliance Semiconductor Corporation.

· Available in 100-pin TQFP and 165-ball BGA package
· Byte write enables
· Clock enable for operation hold
· Multiple chip enables for easy expansion
· 3.3V core power supply
· 2.5V or 3.3V I/O operation with separate V

DDQ

· Self-timed write cycles
· Interleaved or linear burst modes
· Snooze mode for standby operation

Logic block diagram

Selection guide

-200

-166

-133

Units

Minimum cycle time

7.5

Maximum pipelined clock frequency

200

166

133

MHz

Maximum pipelined clock access time

3.0

3.4

3.8

Maximum operating current

370

340

320

Maximum standby current

130

120

110

Maximum CMOS standby current (DC)

L
W
H

X
II
H
U

$GGUHVV

&/.

UHJLVWHU

2XWSXW

UHJLVWHU

'4 >DE@

&/.

&(
&(

$>@

&/.

&(1

&RQWURO

&/.

ORJLF

'DWD

&/.

LQSXW

UHJLVWHU

0 [

65$0

DUUD\

'4 >DE@

%:D
%:E

&/.

$'9 /'

/%2

EXUVW ORJLF

DGGU UHJLVWHUV

:ULWH GHOD\

&/.

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Pin and ball assignment

165-ball BGA - top view

100-pin TQFP - top view

%:E

&(1

ADV/LD

%:D

&/.

''4

'43D

'4E

''4

'4D

'4E

''4

'4D

'4E

''4

'4D

'4E

''4

'4D

'4E

''4

'4D

'4E

''4

'4D

'4E

''4

'4D

'4E

''4

'4D

'43E

''4

7',

1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

7'2

/%2

706

7&.

/%2

$ $ $ $ $ $ 1& 1&

1& 1&

$ $ $ $ $ $

$ $ &( &(

1& 1& %:

&/. 5

&(1 2( $'

$ $ $ $

74)3 [ PP

''4

664

'4E

664

''4

'4E

''4

664

'4E

664

''4

664

'4D

664

''4

'4D

''4

664

'4D

664

''4

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Functional description

The AS7C331MNTD18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as
1,048,576 words × 18 bits and incorporates a LATE LATE Write.

This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD

) architecture, featuring an enhanced write operation

that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied
to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data
to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-
write operations.

NTD

devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-

through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD

write and read operations can be used in any order without producing dead bus cycles.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write
enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles
later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal
operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a
two cycle deselect latency allows pending read or write operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins
are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can
be stalled using the CEN=1, the clock enable input.

The AS7C331MNTD18A operates with a 3.3V ± 5% power supply for the device core (V

). DQ circuits use a separate power supply (V

DDQ

)

that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package and 165 BGA Ball Grid Array package.

Capacitance

Burst order

Parameter

Symbol

Signals

Test conditions

Max

Unit

Input capacitance

Address and control pins

= 0V

I/O capacitance

I/O

I/O pins

= V

out

= 0V

Interleaved burst order LBO = 1

Linear burst order LBO = 0

A1A0

Starting address

0 0

0 1

1 0

1 1

Starting Address

0 0

0 1

1 0

1 1

First increment

0 1

0 0

1 1

1 0

First increment

0 1

1 0

1 1

0 0

Second increment

1 0

1 1

0 0

0 1

Second increment

1 0

1 1

0 0

0 1

Third increment

1 1

1 0

0 1

0 0

Third increment

1 1

0 0

0 1

1 0

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Signal descriptions

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.

Signal

I/O

Properties Description

CLK

CLOCK

Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.

CEN

SYNC

Clock enable. When de-asserted high, the clock input signal is masked.

A, A0, A1

SYNC

Address. Sampled when all chip enables are active and ADV/LD is asserted.

DQ[a,b]

I/O

SYNC

Data. Driven as output when the chip is enabled and OE is active.

CE0, CE1,
CE2

SYNC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is high.

ADV/LD

SYNC

Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.

R/W

SYNC

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.

BW[a,b]

SYNC

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.

ASYNC

Asynchronous output enable. I/O pins are not driven when OE is inactive.

LBO

STATIC

Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This input should be static when the
device is in operation.

STATIC

Flow-through mode.When low, enables single register flow-through mode. Connect to V

if unused or for pipelined operation.

TDO

SYNC

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)

TDI

SYNC

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)

TMS

SYNC

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)

TCK

SYNC

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

No connects.

Parameter

Symbol

Min

Max

Unit

Power supply voltage relative to GND

, V

DDQ

0.5

+4.6

Input voltage relative to GND (input pins)

0.5

+ 0.5

Input voltage relative to GND (I/O pins)

0.5

DDQ

+ 0.5

Power dissipation

1.8

DC output current

OUT

Storage temperature (plastic)

stg

+150

Temperature under bias (junction)

bias

65 +150

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Synchronous truth table

Key: X = don't care, L = low, H = high

State diagram for NTD SRAM

Recommended operating conditions

CE0

CE1

CE2

ADV/LD

R/W

BW[a,b]

CEN

Address source

CLK

Operation

L to H

Deselect, high-Z

L to H

Deselect, high-Z

L to H

Deselect, high-Z

External

L to H

Begin read

External

L to H

Begin write

1 Should be low for burst write unless specific bytes need to be inhibited

Burst counter

L to H

Burst

2 Refer to state diagram below.

Stall

L to H

Inhibit the CLK

Parameter

Symbol

Min

Nominal

Max

Unit

Supply voltage

3.135

3.3

3.465

GND

0.0

3.3V I/O supply voltage

DDQ

2.375

3.3

3.465

GND

0.0

2.5V I/O supply voltage

DDQ

2.35

2.5

2.65

GND

0.0

Input voltages

1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V operation, contact factory for input specifications.

Address and
control pins

2.0

+ 0.3

0.5

2 V

min = 2.0V for pulse width less than 0.2 x t

0.7

I/O pins

2.0

DDQ

+ 0.3

-0.5

0.7

Ambient operating temperature

° C

'VHO

5HDG

%XUVW

:ULWH

5HDG

:ULWH

%XUVW

5HDG

L
W
H

'VHO

5HDG

%XUVW

:ULWH

'VHO

'VH

:ULW

ULWH

%XUVW

'VHO

%XUVW

:ULWH

5HDG

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

DC electrical characteristics for 3.3V I/O operation

DC electrical characteristics for 2.5V I/O operation

Parameter

Sym

Test conditions

200

166

133

Unit

Min

Max

Min

Max

Min

Max

Input leakage current

1 LBO, FTX, and ZZX pins and the 165 BGA JTAG pins (TMSX, TDIX, and TCKX)have an internal pull-up, and input leakage = ±10

| I

= Max, V

= GND to V

-2

µA

Output leakage

current

| I

IH,

= Max,

out

= GND to V

-2

µA

Operating power
supply current

given with no output loading. I

increases with faster cycle times and greater output loading.

CE = V

, CE = V

f = f

max,

out

= 0 mA

370

340

320

Standby power supply
current

Deselected, f = f

max

130

120

110

SB1

Deselected, f = 0,

all V

0.2V or

- 0.2V

SB2

Deselected, f = f

Max

- 0.2V,

all V

Output voltage

= 8 mA, V

DDQ

= 3.6V

0.4

= 4 mA, V

DDQ

= 3.0V

2.4

Parameter

Sym

Test conditions

200

166

133

Unit

Min

Max

Min

Max

Min

Max

Output leakage
current

IH,

= Max,

out

= GND to V

-1

µA

Output voltage

= 2 mA, V

DDQ

= 2.65V

0.7

= 2 mA, V

DDQ

= 2.35V

1.7

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Timing characteristics over operating range

Parameter

Sym

200

166

133

Unit

Notes

1 See "Notes" on page 17

Min

Max

Min

Max

Min

Max

Clock frequency

MAX

200

166

133

MHz

Cycle time (pipelined mode)

CYC

7.5

Cycle time (flow-through mode)

CYCF

7.5

8.5

Clock access time (pipelined mode)

3.0

3.4

3.8

Clock access time (flow-through
mode)

CDF

7.5

8.5

Output enable low to data valid

3.0

3.4

3.8

Clock high to output low Z

LZC

2, 3, 4

Data output invalid from clock high

1.5

Output enable low to output low Z

LZOE

2, 3, 4

Output enable high to output high Z

HZOE

3.0

3.4

3.8

2, 3, 4

Clock high to output high Z

HZC

3.0

3.4

3.8

2, 3, 4

Output enable high to invalid output

OHOE

Clock high pulse width

1.8

2.4

Clock low pulse width

1.8

2.2

2.4

Address and Control setup to clock
high

1.4

1.5

Data setup to clock high

1.4

1.5

Write setup to clock high

1.4

1.5

6, 7

Chip select setup to clock high

CSS

1.4

1.5

6, 8

Address hold from clock high

0.4

0.5

Data hold from clock high

0.4

0.5

Write hold from clock high

0.4

0.5

6, 7

Chip select hold from clock high

CSH

0.4

0.5

6, 8

Clock enable setup to clock high

CENS

1.4

1.5

Clock enable hold from clock high

CENH

0.4

0.5

ADV setup to clock high

ADVS

1.4

1.5

ADV hold from clock high

ADVH

0.4

0.5

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

IEEE 1149.1 serial boundary scan (JTAG)

The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the
critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully
compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels.

The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG feature

If the JTAG function is not being implemented, its pins/balls can be left unconnected. At power-up, the device will come up in a reset state
which will not interfere with the operation of the device.

Test access port (TAP)

Test clock (TCK)

The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.

Test mode select (TMS)

The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the
TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.

83'$7(,5

&$3785(,5

6+,)7,5

(;,7,5

3$86(,5

(;,7,5

6(/(&7

,56&$1

83'$7('5

&$3785('5

6+,)7'5

(;,7'5

3$86('5

(;,7'5

5817(67

,'/(

7(67

/2*,&

6(/(&7

'56&$1

1RWH 7KH RU QH[W WR HDFK VWDWH UHSUHVHQWV WKH YDOXH RI 706 DW WKH ULVLQJ HGJH RI 7&.

TAP controller state diagram

TAP controller block diagram

6HOHFWLRQ

&LUFXLWU\

6HOHFWLRQ

&LUFXLWU\

%RXQGDU\ 6FDQ 5HJLVWHU

,GHQWLILFDWLRQ 5HJLVWHU

%\SDVV 5HJLVWHU

,QVWUXFWLRQ 5HJLVWHU

[

7',

706

7&.

7'2

7$3 &RQWUROOHU

[ IRU WKH [ FRQILJXUDWLRQ [ IRU WKH [

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Test data-in (TDI)

The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between
TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register,
see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram.)

Test data-out (TDO)

The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state
machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP
Controller State Diagram.)

Performing a TAP RESET

You can perform a RESET by forcing TMS high (V

) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and

can be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP registers

Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is
output on the TDO pin/ball on the falling edge of TCK.

Instruction register

You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/
balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the
controller is placed in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault
isolation of the board-level series test data path.

Bypass register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit
register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The
bypass register is set low (Vss) when the BYPASS instruction is executed.

Boundary scan register

The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 70-bit-long
register and the x18 configuration has a 51-bit-long register.

The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and SAMPLE Z
instructions can be used to capture the contents of the I/O ring.

The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM
package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.

Identification (ID) register

The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded with
a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

TAP instruction set

Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of
these instructions are reserved and should not be used.

Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot
preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During
this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is
shifted in, the TAP controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP
controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM
outputs in a high-Z state.

EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1.

IDCODE

The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register
between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller is
in a Shift-DR state. It also places all SRAM outputs into a high-Z state.

SAMPLE/PRELOAD

When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of
data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a 1149.1
mandatory instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore, is not
fully 1149.1 compliant.

Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output
can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the
TAP controller's capture setup plus hold time (t

plus t

). The SRAM clock input might not be captured correctly if there is no way in a

design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and
ignore the value of the CK and CK# captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/
PRELOAD instruction will have the same effect as the Pause-DR command.

BYPASS

The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between
TDI and TDO.

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Reserved

Do not use a reserved instruction.These instructions are not implemented but are reserved for future use.

TAP timing diagram

TAP AC electrical characteristics

For notes 1 and 2, +10

C < T

< +110

C and +2.4V < V

< +2.6V.

Description

Symbol

Min

Max

Units

Clock

Clock cycle time

THTH

100

Clock frequency

MHz

Clock high time

THTL

Clock low time

TLTH

Output Times

TCK low to TDO unknown

TLOX

TCK low to TDO valid

TLOV

TDI valid to TCK high

DVTH

TCK high to TDI invalid

THDX

Setup Times

TMS setup

MVTH

Capture setup

1 t

and t

refer to the setup and hold time requirements of latching data

from the boundary scan register.

Test conditions are specified using the load in the figure TAP AC output

load equivalent.

Hold Times

TMS hold

THMX

Capture hold

7+7/

7/7+

7+7+

097+

7+0;

'97+

7+';

7/2;

7/29

7HVW &ORFN

7&.

7HVW 0RGH 6HOHFW

706

7HVW 'DWD,Q

7',

7HVW 'DWD2XW

7'2

'RQ¶W FDUH

8QGHILQHG

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

3.3V V

, TAP DC electrical characteristics and operating conditions

(+10

C < T

< +110

C and +3.135V < V

< +3.465V unless otherwise noted)

2.5V V

, TAP DC electrical characteristics and operating conditions

(+10

C < T

< +110

C and +2.4V < V

< +2.6V unless otherwise noted)

1. All voltage referenced to V

(GND).

2. Overshoot: V

(AC)

+ 1.5V for t

KHKH

Undershoot: V

(AC)

-0.5 for t

KHKH

Power-up: V

+2.6V and V

2.4V and V

DDQ

1.4V for t

200ms

During normal operation, V

DDQ

must not exceed V

. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than t

KHKL

(Min) or oper-

ate at frequencies exceeding f

(Max).

Description

Conditions

Symbol

Min

Max

Units

Notes

Input high (logic 1) voltage

2.0

+ 0.3

1, 2

Input low (logic 0) voltage

-0.3

0.8

1, 2

Input leakage current

-5.0

5.0

Output leakage current

Outputs disabled,

DDQ

(DQx)

-5.0

5.0

Output low voltage

OLC

= 100

OL1

0.7

Output low voltage

OLT

= 2mA

OL2

0.8

Output high voltage

OHS

= -100

OH1

2.9

Output high voltage

OHT

= -2mA

OH2

2.0

Description

Conditions

Symbol

Min

Max

Units

Notes

Input high (logic 1) voltage

1.7

+ 0.3

1, 2

Input low (logic 0) voltage

-0.3

0.7

1, 2

Input leakage current

-5.0

5.0

Output leakage current

Outputs disabled,

DDQ

(DQx)

-5.0

5.0

Output low voltage

OLC

= 100

OL1

0.2

Output low voltage

OLT

= 2mA

OL2

0.7

Output high voltage

OHS

= -100

OH1

2.1

Output high voltage

OHT

= -2mA

OH2

1.7

Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V

Input rise and fall times. . . . . . . . . . . . . . . 1 ns

Input timing reference levels. . . . . . . . . . 1.25V

Output reference levels . . . . . . . . . . . . . . 1.25V

Test load termination supply voltage. . . . 1.25V

TAP AC test conditions

TAP AC output load equivalent

7'2

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Identification register definitions

Scan register sizes

Instruction codes

Instruction field

1M x 18

Description

Revision number (31:28)

xxxx

Reserved for version number.

Device depth (27:23)

xxxxx

Defines the depth of 1Mb words.

Device width (22:18)

xxxxx

Defines the width of x18 bits.

Device ID (17:12)

xxxxxx

Reserved for future use.

JEDEC ID code (11:1)

00000110100 Allows unique identification of SRAM vendor.

ID register presence indicator (0)

Indicates the presence of an ID register.

Register name

Bit size

Instruction

Bypass

Boundary scan

x18:51

x36:70

Instruction

Code

Description

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high-Z state.

Reserved

011

Do not use. This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.

Reserved

101

Do not use. This instruction is reserved for future use.

Reserved

110

Do not use. This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

AC test conditions

Notes:

1) For test conditions, see "AC test conditions", Figures A, B, C

2) This parameter measured with output load condition in Figure C.

3) This parameter is sampled, but not 100% tested.

4) t

HZOE

is less than t

LZOE

and t

HZC

is less than t

LZC

at any given temperature and voltage.

5) t

measured high above V

and t

measured as low below V

6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.

7) Write refers to

R/W and BW[a,b]

8) Chip select refers to

CE0, CE1, and CE2

287

)LJXUH % 2XWSXW ORDG $

)LJXUH $ ,QSXW ZDYHIRUP

*1'

· Output load: see Figure B, except for t

LZC

, t

LZOE

, t

HZOE

, t

HZC

, see Figure C.

· Input pulse level: GND to 3V. See Figure A.

· Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

· Input and output timing reference levels: 1.5V.

IRU 9 ,2

''4

IRU 9 ,2

7KHYHQLQ HTXLYDOHQW

OUT

*1'

)LJXUH & 2XWSXW ORDG%

LQFOXGLQJ VFRSH

DQG MLJ FDSDFLWDQFH

9 IRU 9 ,2

© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the

trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this

document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is

under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to

operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express

or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as

express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of

products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products

for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems

implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

$6&017'$

Y $GYDQFH ,QIR

$OOLDQFH 6HPLFRQGXFWRU

3 RI

Ordering information

Part numbering guide

1. Alliance Semiconductor SRAM prefix

2. Operating voltage: 33 = 3.3V

3. Organization: 1M

4. NTDTM = No Turn-Around Delay. Pipelined/flow-through mode (each device works in both modes)

5. Organization: 18 = x 18

6. Production version: A = first production version

7. Clock speed (MHz)

8. Package type: TQ = TQFP; B = BGA

9. Operating temperature: C = commercial (0

C to 70

C); I = industrial (-40

C to 85

Package &Width

200 MHz

166 MHz

133 MHz

TQFP x18

AS7C331MNTD18A-200TQC

AS7C331MNTD18A-166TQC

AS7C331MNTD18A-133TQC

AS7C331MNTD18A-200TQI

AS7C331MNTD18A-166TQI

AS7C331MNTD18A-133TQI

BGA x18

AS7C331MNTD18A-200BC

AS7C331MNTD18A-166BC

AS7C331MNTD18A-133BC

AS7C331MNTD18A-200BI

AS7C331MNTD18A-166BI

AS7C331MNTD18A-133BI

AS7C

NTD

XXX

TQ or B

C/I

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS7C331MNTD18A-200BC

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS7C331MNTD18A-200BC

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS7C331MNTD18A-200BC