March 2002
Copyright Alliance Semiconductor. All rights reserved.
AS7C33128PFS32A
AS7C33128PFS36A
3.3V 128K X 32/36 pipeline burst synchronous SRAM
3/4/02; v.1.4
Alliance Semiconductor
P. 1 of 13
Features
Organization: 131,072 words 32 or 36 bits
Fast clock speeds to 200 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
Fully synchronous register-to-register operation
Single register "Flow-through" mode
Single-cycle deselect
Dual-cycle deselect also available (AS7C33128PFD32A/
AS7C33128PFD36A)
Pentium
1
compatible architecture and timing
Asynchronous output enable control
Economical 100-pin TQFP package
Byte write enables
Multiple chip enables for easy expansion
3.3 core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power in power down mode
NTDTM
1
pipeline architecture available
(AS7C33128NTD32A/ AS7C33128NTD36A)
1 Pentium
is a registered trademark of Intel Corporation. NTDTM is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
Q0
Q1
128K 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
D
Q
CE
CLK
DQ
d
CLK
D
Q
Byte write
registers
register
DQ
c
CLK
D
Q
Byte write
registers
DQ
b
CLK
D
Q
Byte write
registers
DQ
a
CLK
D
Q
Byte write
registers
Enable
CLK
D
Q
register
Enable
CLK
D
Q
delay
register
CE
Output
registers
Input
registers
Power
down
4
36/32
17
15
17
17
GWE
BWE
BW
d
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
OE
A[16:0]
ZZ
LBO
OE
FT
CLK
CLK
36/32
36/32
DQ [a:d]
Pin arrangement
DQP
c
/NC
DQ
c
DQ
c
V
DDQ
V
SSQ
DQ
c
DQ
c
DQ
c
DQ
c
V
SSQ
V
DDQ
DQ
c
DQ
c
FT
V
DD
NC
V
SS
DQ
d
DQ
d
V
DDQ
V
SSQ
DQ
d
DQ
d
DQ
d
DQ
d
V
SSQ
V
DDQ
DQ
d
DQ
d
DQP
d
/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
b
/NC
DQ
b
DQ
b
V
DDQ
V
SSQ
DQ
b
DQ
b
DQ
b
DQ
b
V
SSQ
V
DDQ
DQ
b
DQ
b
V
SS
ZZ
DQ
a
DQ
a
V
DDQ
V
SSQ
DQ
a
DQ
a
DQ
a
DQ
a
V
SSQ
V
DDQ
DQ
a
DQ
a
DQP
a
/NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
BW
d
BW
c
BW
b
BW
a
CE2
V
DD
V
SS
CLK
GW
E
BW
E
OE
ADS
C
ADS
P
AD
V
A8
A9
NC
VDD
A1
6
Note: Pins 1,30,51,80 are NC for 32
TQFP 14 20 mm
Selection guide
200
183
166
133
100
Units
Minimum cycle time
5
5.4
6
7.5
10
ns
Maximum clock frequency
200
183
166
133
100
MHz
Maximum pipelined clock access time
3
3.1
3.5
4
5
ns
Maximum operating current
570
540
475
425
325
mA
Maximum standby current
160
140
130
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
30
30
mA
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 2 of 13
Functional description
The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072 words 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.
Timing for these devices is compatible with existing Pentium
synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC
TM
1
-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 5.0/5.4/6.0/7.5/10 ns with clock access times (t
CD
) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 MHz
bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst
addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High.
Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium
count sequence. With
LBO driven LOW, the device uses a linear count sequence suitable for PowerPC
TM
and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate
at 2.5V or 3.3V. These devices are available in a 100-pin 14 20 mm TQFP package.
.H\ X = Don't Care, L = Low, H = High, T = True, F = False; *=
Valid read; n = a, b, c, d; WE, WEn = internal write signal.
1 PowerPC
TM
is a trademark International Business Machines Corporation.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
Address and control pins
V
IN
= 0V
5
pF
I/O capacitance
C
I/O
I/O pins
V
IN
= V
OUT
= 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
L
X
X
T
H
L
L
T
H
H
X
F*
H
L
H
F
*
Burst Order
Interleaved Burst Order
LBO=1
Linear Burst Order
LBO=0
Starting Address
00
01
10
11
Starting Address
00
01
10
11
First increment
01
00
11
10
First increment
01
10
11
00
Second increment
10
11
00
01
Second increment
10
11
00
01
Third increment
11
10
01
00
Third increment
11
00
01
10
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 3 of 13
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Signal descriptions
Signal
I/O
Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
A0A16
I
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b,c,d]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
ADSC
I
SYNC
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
ADV
I
SYNC
Advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
BW[a,b,c,d]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO
I
STATIC
default =
HIGH
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.
18
FT
I
STATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to
V
DD
if unused or for pipelined operation.
ZZ
I
ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
V
DD
, V
DDQ
0.5
+4.6
V
Input voltage relative to GND (input pins)
V
IN
0.5
V
DD
+ 0.5
V
Input voltage relative to GND (I/O pins)
V
IN
0.5
V
DDQ
+ 0.5
V
Power dissipation
P
D
1.8
W
DC output current
I
OUT
50
mA
Storage temperature (plastic)
T
stg
65
+150
o
C
Temperature under bias
T
bias
65 +135
o
C
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 4 of 13
1
See "Write enable truth table" on page 2 for more information.
2
Q in flow through mode.
3
For write operation following a READ,
OE
must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Key: X = Don't Care, L = Low, H = High.
Synchronous truth table
CE0
CE1
CE2
ADSP
ADSC
ADV
WEn
1
OE
Address accessed
CLK
Operation
DQ
H
X
X
X
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
L
X
L
X
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
L
X
H
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
X
H
L
X
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
X
H
H
L
X
X
X
NA
L to H
Deselect
Hi
-
Z
L
H
L
L
X
X
X
L
External
L to H
Begin read
Hi
-
Z
2
L
H
L
L
X
X
X
H
External
L to H
Begin read
Hi
-
Z
L
H
L
H
L
X
F
L
External
L to H
Begin read
Hi
-
Z
2
L
H
L
H
L
X
F
H
External
L to H
Begin read
Hi
-
Z
X
X
X
H
H
L
F
L
Next
L to H
Cont. read
Q
X
X
X
H
H
L
F
H
Next
L to H
Cont. read
Hi
-
Z
X
X
X
H
H
H
F
L
Current
L to H
Suspend read
Q
X
X
X
H
H
H
F
H
Current
L to H
Suspend read
Hi
-
Z
H
X
X
X
H
L
F
L
Next
L to H
Cont. read
Q
H
X
X
X
H
L
F
H
Next
L to H
Cont. read
Hi
-
Z
H
X
X
X
H
H
F
L
Current
L to H
Suspend read
Q
H
X
X
X
H
H
F
H
Current
L to H
Suspend read
Hi
-
Z
L
H
L
H
L
X
T
X
External
L to H
Begin write
D
3
X
X
X
H
H
L
T
X
Next
L to H
Cont. write
D
H
X
X
X
H
L
T
X
Next
L to H
Cont. write
D
X
X
X
H
H
H
T
X
Current
L to H
Suspend write
D
H
X
X
X
H
H
T
X
Current
L to H
Suspend write
D
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 5 of 13
Recommended operating conditions
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
DD
3.135
3.3
3.6
V
V
SS
0.0
0.0
0.0
3.3V I/O supply voltage
V
DDQ
3.135
3.3
3.6
V
V
SSQ
0.0
0.0
0.0
2.5V I/O supply voltage
V
DDQ
2.35
2.5
2.9
V
V
SSQ
0.0
0.0
0.0
Input voltages
1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
Address and
control pins
V
IH
2.0
V
DD
+ 0.3
V
V
IL
0.5
2
2 V
IL
min. = 2.0V for pulse width less than 0.2 t
RC
.
0.8
I/O pins
V
IH
2.0
V
DDQ
+ 0.3
V
V
IL
0.5
2
0.8
Ambient operating temperature
T
A
0
70
C
TQFP thermal resistance
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)
1
1 This parameter is sampled.
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA/
JESD51
JA
46
C/W
Thermal resistance
(junction to top of case)
1
JC
2.8
C/W
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 6 of 13
DC electrical characteristics
Parameter
Symbol
Test conditions
200
183
166
133
100
Unit
Min Max Min Max
Min
Max
Min
Max
Min
Max
Input leakage
current
1
|I
LI
|
V
DD
= Max, V
IN
= GND to V
DD
2
2
2
2
2
A
Output leakage
current
|I
LO
|
OE
V
IH
, V
DD
= Max,
V
OUT
= GND to V
DD
2
2
2
2
2
A
Operating
power supply
current
I
CC
2
CE0 = V
IL
, CE1 = V
IH
, CE2 = V
IL
,
f = f
Max
, I
OUT
= 0 mA
570
540
475
425
325
mA
Standby power
supply current
I
SB
Deselected, f = f
Max
, ZZ
V
IL
160
140
130
100
90
mA
I
SB1
Deselected, f = 0, ZZ
0.2V
all V
IN
0.2V or
V
DD
0.2V
30
30
30
30
30
I
SB2
Deselected, f = f
Max
, ZZ
V
DD
0.2V
All V
IN
V
IL
or
V
IH
30
30
30
30
30
Output voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 3.465V
0.4
0.4
0.4
0.4
0.4
V
V
OH
I
OH
= 4 mA, V
DDQ
= 3.135V
2.4
2.4
2.4
2.4
2.4
1 LBO pin has an internal pull-up and input leakage = 10
a.
2 I
CC
given with no output loading. I
CC
increases with faster cycles times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
Parameter
Symbol
Test conditions
200
183
166
133
100
Unit
Min Max Min Max Min Max Min Max Min Max
Output leakage
current
|I
LO
|
OE
V
IH
, V
DD
= Max,
V
OUT
= GND to V
DD
1
1
1
1
1
1
1
1
1
1
A
Output voltage
V
OL
I
OL
= 2 mA, V
DDQ
= 2.65V
0.7
0.7
0.7
0.7
0.7
V
V
OH
I
OH
= 2 mA, V
DDQ
= 2.35V
1.7
1.7
1.7
1.7
1.7
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 7 of 13
Timing characteristics over operating range
Parameter
Sym
200
183
166
133
100
Unit Notes
1
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock frequency
f
Max
200
183
166
133
100 MHz
Cycle time (pipelined mode)
t
CYC
5
5.4
6
7.5
10
ns
Cycle time (flow-through mode)
t
CYCF
9
10
10
12
12
ns
Clock access time (pipelined mode)
t
CD
3.0
3.1
3.5
4.0
5.0
ns
Clock access time (flow-through mode)
t
CDF
8.5
9
9
10
12
ns
Output enable LOW to data valid
t
OE
3.0
3.1
3.5
4.0
5.0
ns
Clock HIGH to output Low Z
t
LZC
0
0
0
0
0
ns
2,3,4
Data output invalid from clock HIGH
t
OH
1.5
1.5
1.5
1.5
1.5
ns
2
Output enable LOW to output Low Z
t
LZOE
0
0
0
0
0
ns
2,3,4
Output enable HIGH to output High Z
t
HZOE
3.0
3.1
3.5
4.0
4.5
ns
2,3,4
Clock HIGH to output High Z
t
HZC
3.0
3.1
3.5
4.0
5.0
ns
2,3,4
Output enable HIGH to invalid output
t
OHOE
0
0
0
0
0
ns
Clock HIGH pulse width
t
CH
2.2
2.4
2.4
2.5
3.5
ns
5
Clock LOW pulse width
t
CL
2.2
2.4
2.4
2.5
3.5
ns
5
Address setup to clock HIGH
t
AS
1.4
1.4
1.5
1.5
2.0
ns
6
Data setup to clock HIGH
t
DS
1.4
1.4
1.5
1.5
2.0
ns
6
Write setup to clock HIGH
t
WS
1.4
1.4
1.5
1.5
2.0
ns
6,7
Chip select setup to clock HIGH
t
CSS
1.4
1.4
1.5
1.5
2.0
ns
6,8
Address hold from clock HIGH
t
AH
0.5
0.5
0.5
0.5
0.5
ns
6
Data hold from clock HIGH
t
DH
0.5
0.5
0.5
0.5
0.5
ns
6
Write hold from clock HIGH
t
WH
0.5
0.5
0.5
0.5
0.5
ns
6,7
Chip select hold from clock HIGH
t
CSH
0.5
0.5
0.5
0.5
0.5
ns
6,8
ADV setup to clock HIGH
t
ADVS
1.4
1.4
1.5
1.5
2.0
ns
6
ADSP setup to clock HIGH
t
ADSPS
1.4
1.4
1.5
1.5
2.0
ns
6
ADSC setup to clock HIGH
t
ADSCS
1.4
1.4
1.5
1.5
2.0
ns
6
ADV hold from clock HIGH
t
ADVH
0.5
0.5
0.5
0.5
0.5
ns
6
ADSP hold from clock HIGH
t
ADSPH
0.5
0.5
0.5
0.5
0.5
ns
6
ADSC hold from clock HIGH
t
ADSCH
0.5
0.5
0.5
0.5
0.5
ns
6
1
See "Notes" on page 11.
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 8 of 13
Key to switching waveforms
Timing waveform of read cycle
Note: = XOR when
LBO
= HIGH/No Connect; = ADD when
LBO
= LOW.
BW[a:d] is don't care.
Undefined/don't care
Falling input
Rising input
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
D
OUT
t
CSS
t
CSH
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV INSERTS WAIT STATES
Q(A210)
Q(A211)
Q(A3)
Q(A2)
Q(A201)
Q(A301)
Q(A310)
Q(A1)
A2
A1
A3
CE1
(pipelined mode)
D
OUT
Q(A210)
Q(A211)
Q(A3)
Q(A201)
Q(A301)
Q(A310)
Q(A311)
Q(A1)
(flow-through mode)
t
HZC
t
OE
t
LZOE
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 9 of 13
Timing waveform of write cycle
Note: = XOR when
LBO
= HIGH/No Connect; = ADD when
LBO
= LOW.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Data In
t
CSH
t
ADVH
D(A201)
D(A210)
D(A3)
D(A2)
D(A201)
D(A301)
D(A310)
D(A1)
D(A211)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1
A2
A3
t
CH
CE1
BW[a:d]
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 10 of 13
Timing waveform of read/write cycle
Note: = XOR when
LBO
= HIGH/No Connect; = ADD when
LBO
= LOW.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
D
IN
D
OUT
t
LZC
t
ADVH
t
LZOE
t
OE
t
CD
Q(A1)
Q(A301)
D(A2)
Q(A3)
Q(A310)
Q(A311)
A1
A2
A3
CE1
t
HZOE
(pipeline mode)
D
OUT
Q(A1)
Q(A301)
Q(A310)
(flow-through mode)
t
CDF
Q(A311)
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 11 of 13
AC test conditions
Notes
1
For test conditions, see AC Test Conditions, Figures A, B, C.
2
This parameter measured with output load condition in Figure C.
3
This parameter is sampled, but not 100% tested.
4
t
HZOE
is less than t
LZOE
; and t
HZC
is less than t
LZC
at any given temperature and voltage.
5
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
7
Write refers to
GWE, BWE, BW[a:d]
.
8
Chip select refers to
CE0, CE1, CE2.
Z
0
= 50
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Output load: see Figure B, except for t
LZC
, t
LZOE
, t
HZOE
, t
HZC
, see Figure C.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
353
/ 1538
5 pF*
319
/ 1667
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
0.65 nominal
Hd
15.90
16.10
He
21.90
22.10
L
0.45
0.75
L1
1.00 nominal
0
7
Dimensions in millimeters
He
E
Hd
D
b
e
A1 A2
L1
L
c
AS7C33128PFS32A
AS7C33128PFS36A
3/4/02; v.1.4
Alliance Semiconductor
P. 12 of 13
AS7C33128PFS32A
AS7C33128PFS36A
Copyright Alliance Sem iconductor Corporation. All rights reserved. Our three-point logo, our nam e and Intelliwatt are tradem arks or registered tradem arks of Alliance. All other brand and
product nam es m ay be the tradem arks of their respective com panies. Alliance reserves the right to m ake changes to this docum ent and its products at any tim e without notice. Alliance assum es no
responsibility for any errors that m ay appear in this docum ent. The data contained herein represents Alliance's best data and/or estim ates at the tim e of issuance. Alliance reserves the right to
change or correct this data at any tim e, without notice. If the product described herein is under developm ent, significant changes to these specifications are possible. The inform ation in this
product data sheet is intended to be general descriptive inform ation for potential custom ers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
custom er. Alliance does not assum e any responsibility or liability arising out of the application or use of any product described herein, and disclaim s any express or im plied warranties related to
the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, m erchantability, or infringem ent of any intellectual property rights, except as
express agreed to in Alliance's Term s and Conditions of Sale (which are available from Alliance). All sales of Alliance products are m ade exclusively according to Alliance's Term s and
Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, m ask works rights, tradem arks, or any other intellectual property rights
of Alliance or third parties. Alliance does not authorize its products for use as critical com ponents in life-supporting systems where a m alfunction or failure m ay reasonably be expected to result
in significant injury to the user, and the inclusion of Alliance products in such life-supporting system s im plies that the m anufacturer assum es all risk of such use and agrees to indem nify Alliance
against all claim s arising from such use.
3/4/02; v.1.4
Alliance Semiconductor
P. 13 of 13
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 128=128K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: S=Single cycle deselect
6.Organization: 32=x32; 36=x36
7.Production version: A=first production version
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (0
C to 70
C); I=Industrial (-40
C to 85
C)
Ordering information
Package
Width
200 MHz
183 MHz
166 MHz
133 MHz
100 MHz
TQFP
x32
AS7C33128PFS32A-
200TQC
AS7C33128PFS32A-
183TQC
AS7C33128PFS32A-
166TQC
AS7C33128PFS32A-
133TQC
AS7C33128PFS32A-
100TQC
TQFP
x32
AS7C33128PFS32A-
200TQI
AS7C33128PFS32A-
183TQI
AS7C33128PFS32A-
166TQI
AS7C33128PFS32A-
133TQI
AS7C33128PFS32A-
100TQI
TQFP
x36
AS7C33128PFS36A-
200TQC
AS7C33128PFS36A-
183TQC
AS7C33128PFS36A-
166TQC
AS7C33128PFS36A-
133TQC
AS7C33128PFS36A-
100TQC
TQFP
x36
AS7C33128PFS36A-
200TQI
AS7C33128PFS36A-
183TQI
AS7C33128PFS36A-
166TQI
AS7C33128PFS36A-
133TQI
AS7C33128PFS36A-
100TQI
Part numbering guide
AS7C
33
128
PF
S
32/36
A
XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
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