December 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C251MNTF32A
AS7C251MNTF36A
12/23/04, v 1.1
Alliance Semiconductor
P. 1 of 18
2.5V 1M 32/36 Flowthrough SRAM with NTD
TM
Features
Organization: 1,048,576 words 32 or 36 bits
NTD
TM
architecture for efficient bus operation
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time:
3.5/4.0 ns
Fully synchronous operation
Flow-through mode
Asynchronous output enable control
Available in 100-pin TQFP package
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
2.5V core power supply
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
Selection guide
-75
-85
-10
Units
Minimum cycle time
8.5
10
12
ns
Maximum clock access time
7.5
8.5
10
ns
Maximum operating current
325
300
275
mA
Maximum standby current
140
130
130
mA
Maximum CMOS standby current (DC)
90
90
90
mA
W
r
ite Buf
fe
r
Address
D
Q
CLK
register
Output
Buffer
DQ[a,b,c,d]
20
20
CLK
CE0
CE1
CE2
A[19:0]
OE
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
32/36
32/36
OE
1M x 32/36
SRAM
Array
R/W
DQ[a,b,c,d]
BWb
BWd
CLK
Q
D
ADV / LD
LBO
Burst logic
addr. registers
Write delay
20
ZZ
CLK
32/36
32/36
32/36
32/36
BWc
BWa
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 2 of 18
2.5V 32 Mb Synchronous SRAM products list
1,2
1 Core Power Supply: VDD = 2.5V + 0.125V
2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V
PL-SCD
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD
:
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT
:
Flow-through Burst Synchronous SRAM
NTD
1
-PL
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
:
Flow-through Burst Synchronous SRAM with NTD
TM
Org
Part Number
Mode
Speed
2MX18
AS7C252MPFS18A
PL-SCD
200/166/133 MHz
1MX32
AS7C251MPFS32A
PL-SCD
200/166/133 MHz
1MX36
AS7C251MPFS36A
PL-SCD
200/166/133 MHz
2MX18
AS7C252MPFD18A
PL-DCD
200/166/133 MHz
1MX32
AS7C251MPFD32A
PL-DCD
200/166/133 MHz
1MX36
AS7C251MPFD36A
PL-DCD
200/166/133 MHz
2MX18
AS7C252MFT18A
FT
7.5/8.5/10 ns
1MX32
AS7C251MFT32A
FT
7.5/8.5/10 ns
1MX36
AS7C251MFT36A
FT
7.5/8.5/10 ns
2MX18
AS7C252MNTD18A
NTD-PL
200/166/133 MHz
1MX32
AS7C251MNTD32A
NTD-PL
200/166/133 MHz
1MX36
AS7C251MNTD36A
NTD-PL
200/166/133 MHz
2MX18
AS7C252MNTF18A
NTD-FT
7.5/8.5/10 ns
1MX32
AS7C251MNTF32A
NTD-FT
7.5/8.5/10 ns
1MX36
AS7C251MNTF36A
NTD-FT
7.5/8.5/10 ns
1. NTD: No Turnaround Delay. NTD
TM
is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 3 of 18
Pin diagram
100-pin TQFP - top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A A
CE0
CE1
BW
d
BW
c
BW
b
BW
a
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
A
A
A
TQFP 14 x 20mm
A
NC/DQPc
DQc0
DQc1
V
DDQ
V
SSQ
DQc2
DQc3
DQc4
DQc5
V
SSQ
V
DDQ
DQc6
DQc7
V
SS
V
DD
NC
V
SS
DQd0
DQd1
V
DDQ
V
SSQ
DQd2
DQd3
DQd4
DQd5
V
SSQ
V
DDQ
DQd6
DQd7
NC/DQPd
DQPb/NC
DQb7
DQb6
V
DDQ
V
SSQ
DQb5
DQb4
DQb3
DQb2
V
SSQ
V
DDQ
DQb1
DQb0
V
SS
ZZ
DQa7
DQa6
V
DDQ
V
SSQ
DQa5
DQa4
DQa3
DQa2
V
SSQ
V
DDQ
DQa1
DQa0
DQPa/NC
V
DD
NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 4 of 18
Functional Description
The AS7C251MNTF32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory
(SRAM) organized as 1,048,576 words 32 or 36 bits and incorporates a LATE Write.
This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
TM
) architecture, featuring an enhanced
write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one dead cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.
NTD
TM
devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-
through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
With NTD
TM
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 36
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C251MNTF32A/36A operates with a 2.5V 5% power supply for the device core (V
DD
). These devices are
available in 100-pin TQFP package.
TQFP Capacitance
*Guranteed not tested
TQFP thermal resistance
Parameter
Symbol
Test conditions
Min
Max
Unit
Input capacitance
C
IN
*
V
in
= 0V
-
5
pF
I/O capacitance
C
I/O
*
V
in
= V
out
= 0V
-
7
pF
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)
1
1 This parameter is sampled
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
1layer
JA
40
C/W
4layer
JA
22
C/W
Thermal resistance
(junction to top of case)
1
JC
8
C/W
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 5 of 18
Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time t
ZZI
is met. After entering SNOOZE MODE, all inputs except ZZ
become disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successful
complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly,
when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of
SNOOZE MODE.
Signal
I/O Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
I
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1
I
SYNC
Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b,c,d]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
ADV/LD
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. When low, a new address is loaded.
R/W
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
BW[a,b,c,d]
I
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE
I
ASYNC
Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
I
STATIC
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ
I
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
-
No connect
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 6 of 18
Burst order
Synchronous truth table
[5,6,7,8,9,11]
Key: X = Don't Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or more
byte write signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the ini-
tial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application's requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
BW
a enables WRITEs to byte "a" (DQa pins);
BW
b enables WRITEs to byte "b" (DQb pins);
BW
c enables WRITEs to byte "c" (DQc pins);
BW
d
enables WRITEs to byte "d" (DQd pins).
6 All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting
CEN
HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
Interleaved burst order LBO = 1
Linear burst order LBO = 0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
Starting address
0 0
0 1
1 0
1 1
Starting Address
0 0
0 1
1 0
1 1
First increment
0 1
0 0
1 1
1 0
First increment
0 1
1 0
1 1
0 0
Second increment
1 0
1 1
0 0
0 1
Second increment
1 0
1 1
0 0
0 1
Third increment
1 1
1 0
0 1
0 0
Third increment
1 1
0 0
0 1
1 0
CE0 CE1 CE2 ADV/LD R/W
BWn
OE CEN
Address
source
CLK
Operation
DQ
Notes
H
X
X
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
X
H
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
L
X
L
X
X
X
L
NA
L to H
DESELECT Cycle
High-Z
X
X
X
H
X
X
X
L
NA
L to H
CONTINUE DESELECT Cycle
High-Z
1
L
H
L
L
H
X
L
L
External L to H
READ Cycle (Begin Burst)
Q
X
X
X
H
X
X
L
L
Next
L to H
READ Cycle (Continue Burst)
Q
1,10
L
H
L
L
H
X
H
L
External L to H NOP/DUMMY READ (Begin Burst) High-Z
2
X
X
X
H
X
X
H
L
Next
L to H
DUMMY READ (Continue Burst)
High-Z 1,2,10
L
H
L
L
L
L
X
L
External L to H
WRITE CYCLE (Begin Burst)
D
3
X
X
X
H
X
L
X
L
Next
L to H
WRITE CYCLE (Continue Burst)
D
1,3,10
L
H
L
L
L
H
X
L
External L to H NOP/WRITE ABORT (Begin Burst) High-Z
2,3
X
X
X
H
X
H
X
L
Next
L to H
WRITE ABORT (Continue Burst)
High-Z
1,2,3,
10
X
X
X
X
X
X
X
H
Current L to H
INHIBIT CLOCK
-
4
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 7 of 18
State diagram for NTD SRAM
Absolute maximum ratings
Stresses greater than those listed under "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
Recommended operating conditions
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
V
DD
, V
DDQ
0.5
+4.6
V
Input voltage relative to GND (input pins)
V
IN
0.5
V
DD
+ 0.5
V
Input voltage relative to GND (I/O pins)
V
IN
0.5
V
DDQ
+ 0.5
V
Power dissipation
P
d
1.8
W
Short circuit output current
I
OUT
20 mA
Storage temperature
T
stg
65
+150
o
C
Temperature under bias
T
bias
65 +135
o
C
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage for inputs
V
DD
2.375
2.5
2.625
V
Supply voltage for I/O
V
DDQ
2.375
2.5
2.625
V
Ground supply
Vss
0
0
0
V
Dsel
Dsel
Rea
d
Read
Burst
Burst
Read
Writ
Burs
Read
W
r
ite
Dsel
Read
Burst
Write
Dsel
Dse
l
Wri
te
W
rit
e
Burst
Dsel
Burst
Burst
Write
Read
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 8 of 18
DC electrical characteristics
LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = 10
A.
*
V
IH
max < VDD +1.5V for pulse width less than 0.2 X t
CYC
**
V
IL
min = -1.5 for pulse width less than 0.2 X t
CYC
I
DD
operating conditions and maximum limits
Parameter
Sym
Conditions
Min
Max
Unit
Input leakage current
|I
LI
|
V
DD
= Max, 0V < V
IN
< V
DD
-2
2
A
Output leakage current
|I
LO
|
OE
V
IH
, V
DD
= Max, 0V < V
OUT
< V
DDQ
-2
2
A
Input high (logic 1) voltage
V
IH
Address and control pins
1.7*
V
DD
+0.3
V
I/O pins
1.7*
V
DDQ
+0.3
V
Input low (logic 0) voltage
V
IL
Address and control pins
-0.3**
0.7
V
I/O pins
-0.3**
0.7
V
Output high voltage
V
OH
I
OH
= 4 mA, V
DDQ
= 2.375V
1.7
V
Output low voltage
V
OL
I
OL
= 8 mA, V
DDQ
= 2.625V
0.7
V
Parameter
Sym
Conditions
-75
-85
-10
Unit
Operating power supply current
1
1
I
CC
given with no output loading. I
CC
increases with faster cycle times and greater output loading.
I
CC
CE0 < V
IL
, CE1 > V
IH
, CE2 < V
IL
, f = f
Max
,
I
OUT
= 0 mA, ZZ
< V
IL
325
300
275
mA
Standby power supply current
I
SB
All V
IN
0.2V or > V
DD
0.2V, Deselected,
f = f
Max
, ZZ
< V
IL
140
130
130
I
SB1
Deselected, f = 0, ZZ
< 0.2V,
all V
IN
0.2V or V
DD
0.2V
90
90
90
I
SB2
Deselected, f = f
Max
, ZZ
V
DD
0.2V,
all V
IN
V
IL
or
V
IH
80
80
80
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 9 of 18
Timing characteristics over operating range
Snooze Mode Electrical Characteristics
Parameter
Sym
-75
-85
-10
Unit
Notes
1
1
See "Notes" on page 15.
Min
Max
Min
Max
Min
Max
Cycle time
t
CYC
8.5
10
12
ns
Clock access time
t
CD
7.5
8.5
10
ns
Output enable low to data valid
t
OE
3.5
4.0
4.0
ns
Clock high to output low Z
t
LZC
2.5
2.5
2.5
ns
2,3,4
Data Output invalid from clock high
t
OH
2.5
2.5
2.5
ns
2
Output enable low to output low Z
t
LZOE
0
0
0
ns
2,3,4
Output enable high to output high Z
t
HZOE
3.5
4.0
4.0
ns
2,3,4
Clock high to output high Z
t
HZC
4.0
5.0
5.0
ns
2,3,4
Output enable high to invalid output
t
OHOE
0
0
0
ns
Clock high pulse width
t
CH
2.5
3.0
3.0
ns
5
Clock low pulse width
t
CL
2.5
3.0
3.0
ns
5
Address and Control setup to clock high
t
AS
2.0
2.0
2.0
ns
6
Data setup to clock high
t
DS
2.0
2.0
2.0
ns
6
Write setup to clock high
t
WS
2.0
2.0
2.0
ns
6, 7
Chip select setup to clock high
t
CSS
2.0
2.0
2.0
ns
6, 8
Address hold from clock high
t
AH
0.5
0.5
0.5
ns
6
Data hold from clock high
t
DH
0.5
0.5
0.5
ns
6
Write hold from clock high
t
WH
0.5
0.5
0.5
ns
6, 7
Chip select hold from clock high
t
CSH
0.5
0.5
0.5
ns
6, 8
Clock enable setup to clock high
t
CENS
2.0
2.0
2.0
ns
6
Clock enable hold from clock high
t
CENH
0.5
0.5
0.5
ns
6
ADV setup to clock high
t
ADVS
2.0
2.0
2.0
ns
6
ADV hold from clock high
t
ADVH
0.5
0.5
0.5
ns
6
Description
Conditions
Symbol
Min
Max
Units
Current during Snooze Mode
ZZ > V
IH
I
SB2
80
mA
ZZ active to input ignored
t
PDS
2
cycle
ZZ inactive to input sampled
t
PUS
2
cycle
ZZ active to SNOOZE current
t
ZZI
2
cycle
ZZ inactive to exit SNOOZE current
t
RZZI
0
AS7C251MNTF32A/36A
12/23/04, v 1.1
Alliance Semiconductor
P. 10 of 18
Key to switching waveforms
Timing waveform of read cycle
Undefined
Falling input
Rising input
don't care
t
CH
t
CYC
t
CL
t
AS
CLK
CEN
R/W
t
CENH
A1
A2
A3
Address
t
AH
t
CENS
t
WS
t
WH
CE0,CE2
t
ADVS
t
CSH
Dout
CE1
t
ADVH
t
OE
t
LZOE
t
HZOE
Q(A1)
Q(A2Y`10)
Q(A3)
OE
ADV/LD
Q(A2Y`11)
Q(A3Y`01)
Q(A2)
Q(A2Y`01)
t
CSS
Command
READ
Q(A2)
BURST
READ
Q(A201)
BURST
READ
Q(A210)
BURST
READ
Q(A211)
STALL
READ
Q(A3)
BURST
READ
Q(A301)
READ
Q(A1)
DSEL
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P. 11 of 18
Timing waveform of write cycle
BURST
WRITE
D(A301)
t
CH
t
CYC
t
CL
t
AS
CLK
CEN
R/W
t
CENH
A1
A2
A3
Address
t
AH
t
CENS
CE0,CE2
t
ADVS
t
CSH
Din
CE1
t
ADVH
t
HZOE
D(A1)
D(A2)
D(A3)
t
DS
OE
ADV/LD
t
DH
Dout
BWn
Q(n-1)
D(A2Y`01) D(A2Y`10)
D(A2Y`11)
D(A3Y`01)
t
CSS
Command
WRITE
D(A2)
BURST
WRITE
D(A201)
STALL
WRITE
D(A3)
WRITE
D(A1)
DSEL
BURST
WRITE
D(A210)
BURST
WRITE
D(A211)
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P. 12 of 18
Timing waveform of read/write cycle
Note: = XOR when LBO = high/no connect. = ADD when LBO = low.
t
CH
t
CYC
t
CL
t
CENS
t
OH
t
OE
CLK
CEN
CE0, CE2
ADV/LD
R/W
ADDRESS
D/Q
OE
Command
t
HZOE
BWn
A2
A1
A3
A5
A4
A7
A6
D(A1)
D(A5)
Q(A6)
D(A2)
D(A201)
Q(A3)
Q(A4)
Q(A401)
t
CENH
t
DS
t
DH
t
LZC
t
CD
t
HZC
t
LZOE
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A401)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DSEL
t
CSS
t
ADVH
t
WS
t
WH
t
WS
t
WH
CE1
WRITE
D(A1)
WRITE
D(A2)
t
ADVS
t
CSH
t
AS
t
AH
D(A7)
BURST
WRITE
D(A201)
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P. 13 of 18
NOP, stall and deselect cycles
Note: = XOR when LBO = high/no connect; = ADD when LBO = low. OE is low.
CLK
CEN
CE0, CE2
ADV/LD
R/W
Address
D/Q
Command
BWn
A1
A2
Q(A1)
D(A2)
Q(A110)
BURST
Q(A1
01)
STALL
DSEL
BURST
DSEL
WRITE
D(A2)
BURST
NOP
D(A2
01)
WRITE
NOP
D(A3)
A3
READ
Q(A1)
BURST
Q(A1
10)
BURST
D(A2
10)
CE1
Q(A101)
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P. 14 of 18
Timing waveform of snooze mode
CLK
All inputs
ZZ
t
ZZI
I
supply
(except ZZ)
Dout
t
PUS
ZZ recovery cycle
I
SB2
t
RZZI
ZZ setup cycle
Deselect or Read Only
Deselect or Read Only
Normal
operation
Cycle
High-Z
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P. 15 of 18
AC test conditions
Notes
1) For test conditions, see "AC test conditions", Figures A, B, and C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
HZOE
is less than t
LZOE
, and t
HZC
is less than t
LZC
at any given temperature and voltage.
5) t
CH
is measured high above V
IH
, and t
CL
is measured low below V
IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to
R/W and BW[a,b,c,d]
.
8) Chip select refers to
CE0, CE1, and CE2
.
Output load: For t
LZC
, t
LZOE
, t
HZOE
, and t
HZC
, see Figure C. For all others, see Figure B.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
D
OUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
353
/1538
5 pF*
319
/1667
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
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P. 16 of 18
Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
0.65 nominal
Hd
15.85
16.15
He
21.80
22.20
L
0.45
0.75
L1
1.00 nominal
0
7
Dimensions in
millimeters
A1 A2
L1
L
c
He E
Hd
D
b
e
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P. 17 of 18
Ordering information
Notes: Add suffix `N' to the above part number for Lead Free Parts (Ex. AS7C251MNTF32A-75TQCN)
Part numbering guide
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 25 = 2.5V
3. Organization: 1M = 1Meg
4. NTF= No Turn-Around Delay. Flow-through mode
5. Organization: 32 = x 32, 36 = x 36
6. Production version: A = first production version
7. Clock access time: [-75 = 7.5 ns; -85 = 8.5 ns; -10 = 10.0 ns]
8. Package type: TQ = TQFP
9. Operating temperature: C = commercial (
0
C to 70 C); I = industrial (-40 C to 85 C)
10. N = Lead free part
Package &
Width
75
85
10
TQFP x32
AS7C251MNTF32A-75TQC
AS7C251MNTF32A-85TQC
AS7C251MNTF32A-10TQC
AS7C251MNTF32A-75TQI
AS7C251MNTF32A-85TQI
AS7C251MNTF32A-10TQI
TQFP x36
AS7C251MNTF36A-75TQC
AS7C251MNTF36A-85TQC
AS7C251MNTF36A-10TQC
AS7C251MNTF36A-75TQI
AS7C251MNTF36A-85TQI
AS7C251MNTF36A-10TQI
AS7C
25
1M
NTF
32/36
A
XX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright Alliance Semiconductor
All Rights Reserved
Part Number: AS7C251MNTF32A
AS7C251MNTF36A
Document Version: v 1.1
Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or
correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are
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