Document Outline
- Features
- Logic block diagram
- Pin arrangement
- Selection guide
- Functional description
- Absolute maximum ratings
- Truth table
- DC operating characteristics (over the operating range)1
- Capacitance (f = 1MHz, Ta = 25 C, VCC = NOMINAL)2
- Read cycle (over the operating range)3,9
- Key to switching waveforms
- Read waveform 1 (address controlled)3,6,7,9
- Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9
- Write cycle (over the operating range) 11
- Write waveform 1 (WE controlled)11
- Write waveform 2 (CE controlled)11
- AC test conditions
- Notes
- Package dimensions
- Ordering codes
- Part numbering system
March 2004
Copyright Alliance Semiconductor. All rights reserved.
AS7C1026B
5 V 64K X 16 CMOS SRAM
3/26/04, v 1.3
Alliance Semiconductor
P. 1 of 10
Features
Industrial and commercial versions
Organization: 65,536 words 16 bits
Center power and ground pins for low noise
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
Low power consumption: STANDBY
- 55 mW / max CMOS I/O
6 T 0.18 u CMOS technology
Easy memory expansion with
CE
,
OE
inputs
TTL-compatible, three-state I/O
JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
ESD protection
2000 volts
Latch-up current
200 mA
Logic block diagram
64 K 16
Array
OE
CE
WE
Column decoder
Row d
e
cod
e
r
A0
A1
A2
A3
A4
A5
A7
V
CC
GND
A8
A9
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
Control circuit
I/O0I/O7
I/O8I/O15
UB
LB
I/O
buffer
A6
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O13
I/O12
GND
V
CC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
44-Pin SOJ (400 mil), TSOP 2
21
22
A12
NC
UB
LB
I/O15
I/O14
2
A3
3
A2
4
A1
1
A4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A6
A7
OE
A5
AS7C10
26B
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
110
100
90
80
mA
Maximum CMOS standby current
10
10
10
10
mA
AS7C1026B
3/26/04, v 1.3
Alliance Semiconductor
P. 2 of 10
Functional description
The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words
16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns are ideal for
high-performance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is static, then full
standby power is reached (I
SB1
). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on
the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry
standard packages.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key:
H = high, L = low, X = don't care.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on V
CC
relative to GND
V
t1
0.50
+7.0
V
Voltage on any pin relative to GND
V
t2
0.50
V
CC
+0.50
V
Power dissipation
P
D
1.0
W
Storage temperature (plastic)
T
stg
65
+150
C
Ambient temperature with VCC
applied
T
bias
55
+125
C
DC current into outputs (low)
I
OUT
20
mA
Truth table
CE
WE
OE
LB
UB
I/O0I/O7
I/O8I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (I
SB
), I
SBI
)
L
H
L
L
H
D
OUT
High Z
Read I/O0I/O7 (I
CC
)
L
H
L
H
L
High Z
D
OUT
Read I/O8I/O15 (I
CC)
L
H
L
L
L
D
OUT
D
OUT
Read I/O0I/O15 (I
CC
)
L
L
X
L
L
D
IN
D
IN
Write I/O0I/O15 (I
CC
)
L
L
X
L
H
D
IN
High Z
Write I/O0I/O7 (I
CC
)
L
L
X
H
L
High Z
D
IN
Write I/O8I/O15 (I
CC
)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (I
CC
)
AS7C1026B
3/26/04, v 1.3
Alliance Semiconductor
P. 3 of 10
Recommended operating conditions
V
IL
min = -1.0V for pulse width less than 5ns
V
IH
max = V
CC
+2.0V for pulse width less than 5ns.
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
V
CC
4.5
5.0
5.5
V
Input voltage
V
IH
2.2
V
CC
+ 0.5
V
V
IL
0.5
0.8
V
Ambient operating temperature
commercial
T
A
0
70
o
C
industrial
T
A
40
85
o
C
DC operating characteristics (over the operating range)
1
Parameter
Sym
Test conditions
-10
-12
-15
-20
Unit
Min Max Min Max Min Max Min Max
Input leakage current
| I
LI
|
V
CC
= Max,
V
IN
= GND to V
CC
1
1
1
-
1
A
Output leakage current
| I
LO
|
V
CC
= Max, CE = V
IH
,
V
OUT
= GND to V
CC
1
1
1
-
1
A
Operating power supply
current
I
CC
V
CC
= Max,
CE
V
IL
, I
OUT
= 0mA,
f = f
Max
110
100
90
-
80
mA
Standby power supply current
I
SB
V
CC
= Max,
CE
V
IH ,
f = f
Max
50
45
45
40
mA
I
SB1
V
CC
= Max, CE
V
CC
0.2 V,
V
IN
0.2 V or
V
IN
V
CC
0.2 V, f = 0
10
10
10
-
10
mA
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
0.4
0.4
0.4
-
0.4
V
V
OH
I
OH
= 4 mA, V
CC
= Min
2.4
2.4
2.4
2.4
-
V
Capacitance (f = 1MHz, T
a
= 25
C, V
CC
= NOMINAL)
2
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
C
IN
A, CE, WE, OE, LB, UB
V
IN
= 0 V
5
pF
I/O capacitance
C
I/O
I/O
V
IN
= V
OUT
= 0 V
7
pF
AS7C1026B
3/26/04, v 1.3
Alliance Semiconductor
P. 4 of 10
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read cycle (over the operating range)
3,9
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min Max Min Max Min Max Min Max
Read cycle time
t
RC
10
12
15
20
-
ns
Address access time
t
AA
10
12
15
-
20
ns
3
Chip enable (CE) access time
t
ACE
10
12
15
-
20
ns
3
Output enable (OE) access time
t
OE
5
6
7
-
8
ns
Output hold from address change
t
OH
3
3
3
3
-
ns
5
CE low to output in low Z
t
CLZ
3
3
3
3
-
ns
4, 5
CE high to output in high Z
t
CHZ
4
5
6
-
7
ns
4, 5
OE low to output in low Z
t
OLZ
0
0
0
0
-
ns
4, 5
Byte select access time
t
BA
5
6
7
-
8
ns
Byte select Low to low Z
t
BLZ
0
0
0
0
-
ns
4, 5
Byte select High to high Z
t
BHZ
5
6
6
-
7
ns
4, 5
OE high to output in high Z
t
OHZ
4
5
6
-
7
ns
4, 5
Power up time
t
PU
0
0
0
0
-
ns
4, 5
Power down time
t
PD
10
12
15
-
20
ns
4, 5
Undefined output/don't care
Falling input
Rising input
t
OH
t
AA
t
RC
t
OH
Data
OUT
Address
Data valid
Previous data valid
AS7C1026B
3/26/04, v 1.3
Alliance Semiconductor
P. 5 of 10
Read waveform 2 (OE, CE, UB, LB controlled)
3,6,8,9
Write cycle (over the operating range)
11
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min Max Min Max Min Max Min Max
Write cycle time
t
WC
10
12
15
20
-
ns
Chip enable (CE) to write end
t
CW
8
9
10
12
-
ns
Address setup to write end
t
AW
8
9
10
12
-
ns
Address setup time
t
AS
0
0
0
0
-
ns
Write pulse width
t
WP
7
8
9
12
-
ns
Write recovery time
t
WR
0
0
0
0
-
ns
Address hold from end of write
t
AH
0
0
0
0
-
ns
Data valid to write end
t
DW
5
6
8
10
-
ns
Data hold time
t
DH
0
0
0
0
-
ns
5
Write enable to output in high Z
t
WZ
5
6
7
-
8
ns
4, 5
Output active from write end
t
OW
1
1
1
2
-
ns
4, 5
Byte select low to end of write
t
BW
7
8
9
9
-
ns
Data valid
t
RC
t
AA
t
BLZ
t
BA
t
OE
t
OLZ
t
OH
t
OHZ
t
HZ
t
BHZ
t
ACE
t
LZ
Address
OE
CE
LB, UB
Data
IN
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