ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 1 -
GENERAL DESCRIPTION
AKD5701-A is an evaluation board for the portable digital audio 16bit A/D converter, AK5701. AKD5701-A
also has the digital audio interface and can achieve the interface with digital audio systems via
opt-connector.
Ordering guide
AKD5701-A --- Evaluation board for AK5701
(Cable for connecting with printer port of IBM-AT compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
DIT with optical output
RCA connector for an external clock input
10pin Header for serial control interface
AK4114
(DIT)
10pin Header
Control Data
10pin Header
DGND
Opt Out
AK5701
VD
AVDD
DSP 1
DVDD
AGND
MIC
5V
Regulator
3.3V
10pin Header
DSP 2
EXT/BCLK
RIN1/
RIN2
LIN1/
LIN2
EXT/LRCK
CLOCK
GEN
Figure 1. AKD5701-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
AK5701 Evaluation board Rev.0
AKD5701-A
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 2 -
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD and VD are supplied from the regulator.
[REG] (Red) =
5V
[AVDD] (Orange) =
open
[DVDD]
(Orange) =
open
[VD] (Orange) = open (for logic)
[AGND] (Black)
=
0V
:
for
analog
ground
[DGND] (Black)
=
0V
:
for
logic
ground
1-2) When AVDD, DVDD and VD are not supplied from the regulator.
[REG] (Red) = "REG" jack should be open.
[AVDD] (Orange) =
2.4
3.6V : for AVDD of AK5701 (typ. 3.0V)
[DVDD] (Orange) =
1.6
3.6V : for DVDD of AK5701 (typ. 3.0V)
[VD] (Orange) = 2.7
3.6V : for logic (typ. 3.0V)
[AGND] (Black) = 0V : for analog ground
[DGND] (Black)
=
0V
:
for
logic
ground
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches.
(See the followings.)
3) Power on.
The AK5701 and AK4114 should be reset once by bringing SW1, 2 "L" upon power-up.
Evaluation mode
In case of AK5701 evaluation using AK4114, same audio interface format should be set for both AK5701 and
AK4114. About AK5701's audio interface format, refer to datasheet of AK5701. About AK4114's audio
interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of PLL, Master Mode (Default)
(2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
(3) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: BCLK or LRCK pin)
(4) Evaluation of using DIT of AK4114 (opt-connector): EXT, Slave Mode
(5) Slave & Bypass Mode
(6) Bypass Mode
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 3 -
(1) Evaluation of PLL, Master Mode (Default)
*
Connect PORT2
DSP1
with DSP.
Figure below shows PORT2 pin assign.
PORT2
GND
GND
NC
NC
NC
VD
SDTO
LRCK
BCLK
MCKO
a) Set up jumper pins of MCKI clock
When using X'tal as MCKI clock, X'tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can
be set to X1. X'tal of 11.2896MHz (Default) is set on the AKD5701-A.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) is supplied through
an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on JP16 (XTI) and select EXTCLK/BCLK on
JP19 (MCLK_SEL). JP14 (EXT1) and R20 should be properly selected in order to match the output impedance
of the clock generator.
JP16
XTI
JP19
MCLK_SEL
MCKI
JP11
MKFS
EXTCLK
/BCLK
5701-
MCKO
EXTCLK
/BCLK
4114-
MCKO
256fs 512fs 1024fs MCKO
b) Set up jumper pins of BCLK clock
Output frequency (32fs/64fs) of BCLK should be set by "BCKO1-0 bit" in the AK5701.
There is no necessity for set up JP12.
JP12
BCLK
32fs 16fs
64fs
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
c) Set up jumper pins of LRCK clock
JP13
LRCK
1fs
2fs
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 4 -
(2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
*
Connect PORT4 (DSP2) with DSP.
Figure below shows PORT4 pin assign.
PORT4
GND
GND
NC
NC
SDTO
VD
EXSDTI
EXLRCK
EXBCLK
MCKI
a) Set up jumper pins of MCKI clock
X'tal of 11.2896MHz (Default) is set on the AKD5701-A. In this case, the AK5701 corresponds to PLL
reference clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5701 is
supplied to a divider (U3: 74VHC4040), EXBCLK and LRCK clocks are generated by the divider. Then
"MCKO bit" in the AK5701 should be set to "1".
When an external clock is supplied through an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on
JP16 (XTI) and select EXTCLK/BCLK on JP17 (MCLK_SEL). JP14 (EXT1) and R20 should be properly
selected in order too match the output impedance of the clock generator.
JP16
XTI
JP19
MCLK_SEL
MCKI
JP11
MKFS
EXTCLK
/BCLK
5701-
MCKO
EXTCLK
/BCLK
4114-
MCKO
256fs 512fs 1024fs MCKO
b) Set up jumper pins of BCLK clock
JP12
BCLK
32fs 16fs
64fs
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
c) Set up jumper pins of LRCK clock
JP13
LRCK
1fs
2fs
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 5 -
(2-a) In the case of using AK4114.
*This mode is BCLK=64fs, LRCK=1fs only.
Set up jumper pins of MCKI clock
*In the case of using X1, JP16 should be open.
JP16
XTI
JP19
MCLK_SEL
JP11
MKFS
EXT
5701
EXT
4114
256fs 512fs 1024fs MCKO
Set up jumper pins of BCLK clock
JP13
LRCK
1fs
2fs
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
Set up jumper pins of LRCK clock
JP12
BCLK
32fs 16fs
64fs
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 6 -
(3) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: BCLK or LRCK pin)
*
Connect PORT4 (DSP2) with DSP.
Figure below shows PORT4 pin assign.
PORT4
GND
GND
NC
NC
SDTO
VD
EXSDTI
EXLRCK
EXBCLK
MCKI
a) Set up jumper pins of MCKI clock
JP16
XTI
JP19
MCLK_SEL
MCKI
EXTCLK
/BCLK
5701-
MCKO
EXTCLK
/BCLK
4114-
MCKO
b) Set up jumper pins of BCLK clock
When an external clock is supplied through a RCA connector J3 (EXT/BCLK), J4 (EXT/LRCK), JP14 (EXT1)
and R20, JP15 (EXT2) and R21 should be properly selected in order to much the output impedance of the clock
generator.
JP12
BCLK
32fs 16fs
64fs
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
c) Set up jumper pins of LRCK clock
JP13
LRCK
1fs
2fs
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 7 -
(4) Evaluation of EXT, Slave Mode
*
Connect PORT4 (DSP2) with DSP.
Figure below shows PORT4 pin assign.
PORT4
GND
GND
NC
NC
SDTO
VD
EXSDTI
EXLRCK
EXBCLK
MCKI
a) Set up jumper pins of MCKI clock
PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open.
b) Set up jumper pins of BCLK clock
JP12
BCLK
32fs 16fs
64fs
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
c) Set up jumper pins of LRCK clock
JP13
LRCK
1fs
2fs
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
d) Set up jumper pins of DATA
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 8 -
(5) Slave & Bypass Mode
*
Connect PORT4 (DSP2) and PORT2 (DSP1) with DSP.
Figure below shows PORT4 and PORT2 pin assign.
PORT4
GND
GND
NC
NC
SDTO
VD
EXSDTI
EXLRCK
EXBCLK
MCKI
PORT2
GND
GND
NC
NC
NC
VD
SDTO
LRCK
BCLK
MCKO
a) Set up jumper pins of MCKI clock
PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open.
b) Set up jumper pins of BCLK clock
JP12
BCLK
32fs 16fs
64fs
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
c) Set up jumper pins of LRCK clock
JP13
LRCK
1fs
2fs
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
d) Set up jumper pins of DATA
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 9 -
(6) Bypass Mode
* Connect PORT4 (DSP2) and PORT2 (DSP1) with DSP.
Figure below shows PORT4 and PORT2 pin assign.
PORT4
GND
GND
NC
NC
SDTO
VD
EXSDTI
EXLRCK
EXBCLK
MCKI
PORT2
GND
GND
NC
NC
NC
VD
SDTO
LRCK
BCLK
MCKO
a) Set up jumper pins of MCKI clock
PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open.
b) Set up jumper pins of BCLK clock
JP12
BCLK
32fs 16fs
64fs
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
c) Set up jumper pins of LRCK clock
JP13
LRCK
1fs
2fs
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
d) Set up jumper pins of DATA
EXT
JP18
LRCK_SEL
LRCK/
DIT
EXTLRCK/
DIT
EXT
LRCK
EXT
JP17
BCLK_SEL
BCLK/
DIT
EXTBCLK/
DIT
EXT
BCLK
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 10 -
DIP Switch set up
[SW2] (MODE): Mode Setting of AK4114
ON is "H", OFF is "L".
No.
Name
ON ("H")
OFF ("L")
1 DIF0
2 DIF1
AK4114 Audio Format Setting
See Table 2
3 OCKS0
4 OCKS1
Master Clock Frequency Select
See Table 3
Table 1. Mode Setting
Resistor for AK5701
Set up for AK4114 SW3
M/S DIF1 DIF0
DIF1
DIF0
DAUX
0
1
0
0
0
24bit, Left justified
Master
0 1 1 0 1
24bit,
I
2
S Master
Default
1
1
0
1
0
24bit, Left justified
Slave
1 1 1 1 1
24bit,
I
2
S Slave
Table 2. Setting for AK5701 and AK4114 Audio Interface Format
No. OCKS1 OCKS0
MCKO1
X'tal
0 0 0 256fs 256fs
Default
2 1 0 512fs 512fs
Table 3. Master Clock Frequency Select for AK4114 (Stereo mode)
Other jumper pins set up
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 11 -
1. JP1 (GND) : Analog ground and Digital ground
OPEN : Separated.
SHORT
:
Common.
(The
connector "DGND" should be open.) <Default>
2. JP2 (AVDD_SEL) : AVDD of the AK5701
OPEN : AVDD is supplied from the regulator ("AVDD" jack should be open). < Default >
SHORT : AVDD is supplied from "AVDD " jack.
3. JP3 (DVDD_SEL) : DVDD of the AK5701
AVDD : DVDD is supplied from "AVDD". < Default >
DVDD : DVDD is supplied from "DVDD " jack.
4. JP4 (CSP) : CSP signal Select (Hi or Low)
H : CSP= "Hi"
L : CSP= "Low"< Default >
5. JP5, JP6 (MPWR) : Connect to MPWR
OPEN : No connect< Default >
SHORT
:
Connect
6. JP7 (LVC_SEL) : Supply line selection of Logic block of LVC.
DVDD : Logic block of LVC is supplied from "DVDD". < Default >
VD : Logic block of LVC is supplied from "VD " jack.
7. JP20 (SDTO) : Select #4 pin of the PORT4 (DSP)
OPEN :
Input
data
for
EXSDTI<Default>
SHORT
:
Output
data
for
SDTO
of
the
PORT4
8. JP8 (CCLK) : CCLK select
OPEN : No connect
SHORT
:
CCLK
connect
<Default>
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 12 -
The function of the toggle SW
[SW1] (DIT): Power control of AK4114. Keep "H" during normal operation.
Keep "L" when AK4114 is not used.
[SW3] (PDN): Power control of AK5701. Keep "H" during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK5701 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(CTRL) with PC by 10-wire flat cable packed with the AKD5701-A
10pin Header
CSN
10 Wire Flat Cable
CCLK
CDTI
10pin Connector
PC
Connect
AKD5701-A
Figure 2. Connect of 10 wire flat cable
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 13 -
Analog Input / Output Circuits
(1) Input Circuits
a) LIN, RIN, MIC Input Circuit
LIN1
J1
MR-552LS
LIN
3
2
LIN2
JP9
LIN
LIN2
LIN1
RIN1
J2
MR-552LS
2
RIN
3
RIN2
JP10
RIN
RIN2
RIN1
1
1
4
6
3
J5
MIC
R38
(Open)
R39
(Open)
Figure 3. LIN, RIN, MIC Input Circuit
(a-1) LIN1, RIN1 input
JP9
LIN
LIN2
LIN1
RIN2
RIN1
RIN
JP10
(a-2) LIN2, RIN2 input
JP9
LIN
LIN2
LIN1
RIN2
RIN1
RIN
JP10
AKM assumes no responsibility for the trouble when using the above circuit examples.
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 14 -
2. Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD5701-A according to previous term.
2. Connect IBM-AT compatible PC with AKD5701-A by 10-line type flat cable (packed with AKD5701-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software".
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled "AK5701 Evaluation Kit" into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of "akd5701-a.exe" to set up the control program.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click "Port Reset" button.
3. Click "Write default" button
Explanation of each buttons
1. [Port Reset] : Set up the USB interface board (AKDUSBIF-A) when using the board.
2. [Write default] : Initialize the register of AK5701-A.
3. [All Write] : Write all registers that is currently displayed.
4. [Function1] : Dialog to write data by keyboard operation.
5. [Function2] : Dialog to write data by keyboard operation.
6. [Function3] : The sequence of register setting can be set and executed.
7. [Function4] : The sequence that is created on [Function3] can be assigned to buttons and executed.
8. [Function5]: The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
9. [SAVE] : Save the current register setting.
10. [OPEN] : Write the saved values to all register.
11. [Write] : Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the
part that is not defined in the datasheet.
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 15 -
Explanation of each dialog
1. [Write
Dialog]
: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes "H" or "1". If not, "L" or "0".
If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog]
:
Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box: Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog]
:
Dialog to evaluate IVOL
There are dialogs corresponding to register of 18h and 19h.
Address Box: Input registers address in 2 figures of hexadecimal.
Start Data Box: Input starts data in 2 figures of hexadecimal.
End Data Box: Input end data in 2 figures of hexadecimal.
Interval Box: Data is written to AK5701 by this interval.
Step Box: Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button.
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 16 -
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
"akr".
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is "akr".
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK5701. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 17 -
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button. The following is displayed.
(2) Set the control sequence.
Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file
name is "aks".
Figure 1. Window of [F3]
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 18 -
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 2 opens.
Figure 2. [F4] window
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 19 -
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is
"DAC_Stereo_ON.aks")
Figure 3. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name
is "*.ak4".
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 20 -
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed.
When [F5] button is clicked, the window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is
"DAC_Output.akr")
(2) Click [WRITE] button, then the register setting is executed.
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 21 -
Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is "*.ak5".
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 22 -
MEASUREMENT RESULTS
1.AK5701 Mode: EXT mode (Slave)
[Measurement condition]
Measurement unit: AP2 (Audio Precision, System two, Cascade)
MCKI: 256fs
BCLK: 64fs
Bit: 16bit
Sampling Frequency: 44.1kHz
Measurement Frequency: 20 20kHz
Power Supply: AVDD=DVDD=VD=3.0V
Temperature: Room
Input Frequency: 1kHz
[Measurement Results]
1.ADC characteristics (MIC Gain = 0dB, IVOL=0dB, ALC = OFF, LIN/RIN ADC)
Result
MGAIN=0dB
MGAIN=+15dB
LIN RIN LIN RIN
S/(N+D)
(-0.5dBFS) 79.0dB 79.0dB 78.3dB 78.4dB
D-Range
(-60dBFS) 89.8dB 89.8dB 87.7dB 87.7dB
S/N
89.9dB 89.8dB 87.7dB 87.7dB
2.AK5701 Mode: PLL MASTER mode
[Measurement condition]
Measurement unit: AP2 (Audio Precision, System two, Cascade)
MCKI: 12MHz
BCLK: 64fs
Bit: 16bit
Sampling Frequency: 44.0995kHz
Measurement Frequency: 20 20kHz
Power Supply: AVDD=DVDD=VD=3.0V
Temperature: Room
Input Frequency: 1kHz
[Measurement Results]
ADC characteristics
Result
MGAIN=0dB
MGAIN=+15dB
LIN RIN LIN RIN
S/(N+D)
(-0.5dBFS) 78.7dB 78.3dB 77.9dB 77.5dB
D-Range
(-60dBFS) 89.3dB 89.3dB 87.4dB 87.3dB
S/N
89.3dB 89.3dB 87.4dB 87.3dB
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 23 -
3.Plot data
[Gain = 0dB]
AKM
AK5701 THD+N vs Input Level (fin=1kHz, GAIN=0dB)
-100
-60
-96
-92
-88
-84
-80
-76
-72
-68
-64
d
B
F
S
-120
-10
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
Figure 1. THD+N vs. Input Level
AKM
AK5701 THD+N vs Frequency (fin=1kHz, GAIN=0dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-100
-60
-96
-92
-88
-84
-80
-76
-72
-68
-64
d
B
F
S
Figure 2. THD+N vs. Input Frequency
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 24 -
AKM
AK5701 Linearity (fin=1kHz, GAIN=0dB)
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
-120
+0
-108
-96
-84
-72
-60
-48
-36
-24
-12
d
B
F
S
TT T T
T
Figure 3. Linearity
AKM
AK5701 Freqency Responce (fin=1kHz, GAIN=0dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-2
+0
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
d
B
F
S
Figure 4. Frequency Response
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 25 -
AKM
AK5701 Crosstalk (fin=1kHz, GAIN=0dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-140
-60
-132
-124
-116
-108
-100
-92
-84
-76
-68
d
B
T T T T T T T T T
T
T
T
T
T
T
T T
T T T
T
T
T T
T
T
Figure 5. Crosstalk
AKM
AK5701 FFT S/(N+D) -0.5dBFS (fin=1kHz, GAIN=0dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-160
-0
-144
-128
-112
-96
-80
-64
-48
-32
-16
d
B
F
S
Figure 6. FFT Plot
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 26 -
AKM
AK5701 FFT DR (fin=1kHz, GAIN=0dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-160
-0
-144
-128
-112
-96
-80
-64
-48
-32
-16
d
B
F
S
Figure 7. FFT Plot
AKM
AK5701 FFT S/N MGAIN=0dB
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-160
+0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
Figure 8. FFT Plot
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 27 -
[Gain = +15dB]
AKM
AK5701 THD+N vs Input Level MGAIN=+15dB
-120
-10
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
dBr
-100
-60
-96
-92
-88
-84
-80
-76
-72
-68
-64
d
B
F
S
Figure 9. THD+N vs. Input Level
AKM
AK5701 THD+N vs Freqency (fin=1kHz, GAIN=+15dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-100
-60
-96
-92
-88
-84
-80
-76
-72
-68
-64
d
B
F
S
Figure 10. THD+N vs. Input Frequency
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 28 -
AKM
AK5701 Lineearity (fin=1kHz, GAIN=+15dB)
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
-120
+0
-108
-96
-84
-72
-60
-48
-36
-24
-12
d
B
F
S
T
TT
Figure 11. Linearity
AKM
AK5701 Freqency Responce (fin=1kHz, GAIN=+15dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-2
+0
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
d
B
F
S
Figure 12.Freqency Response
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 29 -
AKM
AK5701 Crosstalk (fin=1kHz, GAIN=+15dB)
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-140
-60
-132
-124
-116
-108
-100
-92
-84
-76
-68
d
B
T T T T T T T T T
T T
T
T T
T T T T T T T T T
T
T
T T
T T
T
Figure 13.Crosstalk
AKM
AK5701 FFT S/(N+D) -0.5dBFS MGAIN=+15dB
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-160
+0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
Figure 14. FFT Plot
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 30 -
AKM
AK5701 FFT DR MGAIN=+15dB
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-160
+0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
Figure 15. FFT Plot
AKM
AK5701 FFT S/N MGAIN=+15dB
20
20k
50
100
200
500
1k
2k
5k
10k
Hz
-160
+0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
Figure 16. FFT Plot
ASAHI KASEI
[AKD5701-A]
<KM076903>
2005/04
- 31 -
Revision History
Date Manual
Revision
Board
Revision
Reason Contents
05/04/25 KM076903
0 First
Edition
IMPORTANT NOTICE
These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
A
A
B
B
C
C
D
D
E
E
E
E
D
D
C
C
B
B
A
A
REG_IN
AVDD1
DVDD1
VD1
REG_IN
AVDD1
DVDD1
VD1
CCLK
AVDD
CDTI
CSN
AVDD
DVDD
VD
DVDD
MCKO
SDTO
5701_M
CKI
AVDD
5701_EXSDTI
5701_EXLRCK
5701_EXBCLK
PDN
LIN1
RIN1
LIN2
RIN2
LVC
BCLK
LRCK
Title
Size
Document Number
Rev
Date:
Sheet
of
AK5701
0
AKD5701-A
A3
1
5
Tuesday, December 14, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
AK5701
0
AKD5701-A
A3
1
5
Tuesday, December 14, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
AK5701
0
AKD5701-A
A3
1
5
Tuesday, December 14, 2004
REG
DVDD
AVDD
H
L
DVDD
VD
R9
51
R9
51
R13
51
R13
51
IN
OUT
GND
T1
TA48033F
T1
TA48033F
JP5
MPWR
JP5
MPWR
1
2
+
C12
47u
+
C12
47u
JP3
DVDD_SEL
JP3
DVDD_SEL
1
2
+
C17
1u
+
C17
1u
1
2
3
4
5
6
CN1
24pin_1
CN1
24pin_1
1
2
+
C6
10u
+
C6
10u
R5
51
R5
51
R10 2.2k
R10 2.2k
JP1
GND
JP1
GND
1
2
+
C14
1u
+
C14
1u
R2
51
R2
51
JP6
MPWR
JP6
MPWR
C2
0.1u
C2
0.1u
R16
51
R16
51
13
14
15
16
17
18
CN3
24pin_3
CN3
24pin_3
C10
0.1u
C10
0.1u
R6
51
R6
51
R18 (open)
R18 (open)
JP7
LVC_SEL
JP7
LVC_SEL
R12
51
R12
51
1
VD1
T45_O
VD1
T45_O
C13 4.7n
C13 4.7n
1
2
+
C18
47u
+
C18
47u
1
2
+
C7
2.2u
+
C7
2.2u
1
REG1
T45_R
REG1
T45_R
R40
51
R40
51
C11 (open)
C11 (open)
JP8
CCLK
JP8
CCLK
JP4
CSP
JP4
CSP
7
8
9
10
11
12
CN2
24pin_2
CN2
24pin_2
1
2
+
C15
1u
+
C15
1u
1
2
+
C5
10u
+
C5
10u
24
23
22
21
20
19
CN4
24pin_4
CN4
24pin_4
C9
0.1u
C9
0.1u
1
2
L3
(short)
L3
(short)
R1
5.1
R1
5.1
R11 2.2k
R11 2.2k
C1
0.1u
C1
0.1u
1
2
L2
(short)
L2
(short)
R15
51
R15
51
JP2
AVDD_SEL
JP2
AVDD_SEL
R7
51
R7
51
1
AGND1
T45_BK
AGND1
T45_BK
1
DVDD1
T45_O
DVDD1
T45_O
1
2
+
C3
47u
+
C3
47u
R8
51
R8
51
1
2
+
C4
47u
+
C4
47u
1
2
L1
(short)
L1
(short)
VCOC
24
VC
O
M
1
AVSS
2
AVD
D
3
DV
DD
4
DV
S
S
5
BC
L
K
6
MC
KI
14
CDT
I
15
CCLK
16
CS
N
17
PD
N
18
EXBC
L
K
13
LIN1
23
RIN1
22
LIN2
21
RIN2
20
MPWR
19
LRCK
7
SDTO
8
CSP
9
MCKO
10
EXSDTI
11
EXLRCK
12
AK5701
U1
AK5701
U1
R4
10k
R4
10k
C8
0.1u
C8
0.1u
R17 (open)
R17 (open)
R14
51
R14
51
1
2
+
C16
1u
+
C16
1u
1
DGND1
T45_BK
DGND1
T45_BK
1
AVDD1
T45_O
AVDD1
T45_O
R3
51
R3
51
A
A
B
B
C
C
D
D
E
E
E
E
D
D
C
C
B
B
A
A
LIN1
LIN2
RIN1
RIN2
Title
Size
Document Number
Rev
Date:
Sheet
of
Input
0
AKD5701-A
A3
2
5
Tuesday, December 14, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
Input
0
AKD5701-A
A3
2
5
Tuesday, December 14, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
Input
0
AKD5701-A
A3
2
5
Tuesday, December 14, 2004
LIN
LIN1
LIN2
RIN
RIN1
RIN2
JP9
LIN
JP9
LIN
R39
(Open)
R39
(Open)
2
3
1
J2
MR-552LS
J2
MR-552LS
JP10
RIN
JP10
RIN
6
4
3
J5
MIC
J5
MIC
R38
(Open)
R38
(Open)
2
3
1
J1
MR-552LS
J1
MR-552LS
A
A
B
B
C
C
D
D
E
E
E
E
D
D
C
C
B
B
A
A
VD
VD
EXT_BCLK
MCKO
MCKI
EXT_LRCK
VD
EXTCLK/LRCK
EXTCLK/BCLK
EXT_MCLK
LVC
Title
Size
Document Number
Rev
Date:
Sheet
of
CLOCK
0
AKD5701-A
A3
3
5
Friday, January 28, 2005
Title
Size
Document Number
Rev
Date:
Sheet
of
CLOCK
0
AKD5701-A
A3
3
5
Friday, January 28, 2005
Title
Size
Document Number
Rev
Date:
Sheet
of
CLOCK
0
AKD5701-A
A3
3
5
Friday, January 28, 2005
1024fs
64fs
512fs
256fs
32fs
16fs
1fs
for
74AC74,74VHC4040,74HC14
MCKO
EXT/BCLK
AVSS
EXT/LRCK
2fs
for
74LVC07ANS
D
2
CLK
3
Q
5
Q
6
PR
4
CL
1
U3A
74AC74
U3A
74AC74
JP11
MKFS
JP11
MKFS
C22
0.1u
C22
0.1u
2
3
1
J3
MR-552LS
J3
MR-552LS
JP12
BLCK_SEL
JP12
BLCK_SEL
R20
51
R20
51
R21
51
R21
51
JP13
LRCK_SEL
JP13
LRCK_SEL
R19
short
R19
short
2
3
1
J4
MR-552LS
J4
MR-552LS
D
12
CLK
11
Q
9
Q
8
PR
10
CL
13
U3B
74AC74
U3B
74AC74
C20
0.1u
C20
0.1u
1
2
+
C23
47u
+
C23
47u
JP14
EXT1
JP14
EXT1
CLK
10
RST
11
Q1
9
Q2
7
Q3
6
Q4
5
Q5
3
Q6
2
Q7
4
Q8
13
Q9
12
Q10
14
Q11
15
Q12
1
U2
74VHC4040
U2
74VHC4040
C19
0.1u
C19
0.1u
C21
0.1u
C21
0.1u
JP15
EXT2
JP15
EXT2
A
A
B
B
C
C
D
D
E
E
E
E
D
D
C
C
B
B
A
A
DAUX
VD
VD
VD
OCKS0
OCKS1
VD
VD
VD
VD
VD
OCKS1
OCKS0
4114_M
CKO
EXTCLK/BCLK
5701_MCKO
4114_BICK
4114_LRCK
Title
Size
Document Number
Rev
Date:
Sheet
of
DIT
0
AKD5701-A
A3
4
5
Thursday, December 02, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
DIT
0
AKD5701-A
A3
4
5
Thursday, December 02, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
DIT
0
AKD5701-A
A3
4
5
Thursday, December 02, 2004
H
L
DIF0
OCKS1
DIF1
OCKS0
1
2
+
C24
10u
+
C24
10u
C27
0.47u
C27
0.47u
IPS0
1
NC
2
DIF0
3
TEST2
4
DIF1
5
NC
6
DIF2
7
IPS1
8
P/SN
9
XTL0
10
XTL1
11
TVD
D
13
D
VSS
14
TX0
15
TX1
16
BO
U
T
17
COUT
18
UOUT
19
VO
U
T
20
DV
DD
21
D
VSS
22
MC
KO1
23
BICK
26
MCKO2
27
DAUX
28
XTO
29
XTI
30
PDN
31
CM0
32
CM1
33
OCKS1
34
OCKS0
35
INT0
36
AVD
D
38
R
39
VC
O
M
40
AVSS
41
RX
0
42
NC
43
RX
1
44
TEST1
45
RX
2
46
NC
47
RX
3
48
VIN
12
LRCK
24
SDTO
25
IN
T1
37
U5
AK4114
U5
AK4114
C26
0.1u
C26
0.1u
1
2
+
C32
10u
+
C32
10u
K
A
D1
HSU119
D1
HSU119
C30
0.1u
C30
0.1u
C34
0.1u
C34
0.1u
C29
(open)
C29
(open)
1
2
+
C33
10u
+
C33
10u
C31
0.1u
C31
0.1u
C28(open)
C28(open)
C25
0.1u
C25
0.1u
1
2
3
4
8
7
6
5
SW2
MODE2
SW2
MODE2
R24
1k
R24
1k
1
2
U4A
74HC14
U4A
74HC14
1
2
X1
11.2896MHz
X1
11.2896MHz
K
A
LED1
ERF
LED1
ERF
R23
18k
R23
18k
R22
10k
R22
10k
JP16 XTI
JP16 XTI
3
4
U4B
74HC14
U4B
74HC14
2
1
3
SW1
DIT
SW1
DIT
GND
1
VCC
2
IN
3
PORT1
TOTX141
PORT1
TOTX141
5
6
U4C
74HC14
U4C
74HC14
1
2
3
4
5
RP1
47k
RP1
47k
A
A
B
B
C
C
D
D
E
E
E
E
D
D
C
C
B
B
A
A
5701_EXSDTI
5701_EXLRCK
5701_EXBCLK
EXT_BCLK
4114_LRCK
EXT_LRCK
4114_BICK
VD
LVC
VD
VD
5701_MCKI
CSN
CCLK
CDTI
PDN
VD
DAUX
4114_MCKO
EXSDTI
BCLK
LRCK
SDTO
MCKO
5701_MCKO
EXSDTI
EXTCLK/LRCK
VD
MCKI
EXTCLK/BCLK
EXT_MCLK
EXTCLK/BCLK
Title
Size
Document Number
Rev
Date:
Sheet
of
LOGIC
0
AKD5701-A
A3
5
5
Friday, December 17, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
LOGIC
0
AKD5701-A
A3
5
5
Friday, December 17, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
LOGIC
0
AKD5701-A
A3
5
5
Friday, December 17, 2004
EXLRCK
EXT
MCKI
VD
EXSDTI
EXBCLK
CCLK
CDTI
CSN
L
H
EXT
EXBCLK-DIT
MCKI
BCLK
LRCK
VD
SDTO
BCLK-DIT
EXTLRCLK
EXLRCK-DIT
LRCK-DIT
SDTO
EXTBCLK
1
2
3
4
5
6
7
8
9
10
PORT4
DSP2
PORT4
DSP2
C35
0.1u
C35
0.1u
R28
330
R28
330
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G1
1
G2
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
VCC
20
GND
10
U6
74LVC541
U6
74LVC541
JP17
BCLK_SEL
JP17
BCLK_SEL
9
8
U4D
74HC14
U4D
74HC14
1
2
U7A
74LVC07ANS
U7A
74LVC07ANS
C37
0.1u
C37
0.1u
R36
10k
R36
10k
R30
10k
R30
10k
11
10
U4E
74HC14
U4E
74HC14
13
12
U7F
74LVC07ANS
U7F
74LVC07ANS
1
2
+
C36
47u
+
C36
47u
JP18
LRCK_SEL
JP18
LRCK_SEL
3
4
U7B
74LVC07ANS
U7B
74LVC07ANS
R29
10k
R29
10k
R26
330
R26
330
2
1
3
SW3
PDN
SW3
PDN
11
10
U7E
74LVC07ANS
U7E
74LVC07ANS
R32
470
R32
470
5
6
U7C
74LVC07ANS
U7C
74LVC07ANS
13
12
U4F
74HC14
U4F
74HC14
JP20
SDTO
JP20
SDTO
R35
470
R35
470
R34
470
R34
470
R31
10k
R31
10k
JP19
MCKI_SEL
JP19
MCKI_SEL
1
2
3
4
5
6
7
8
9
10
PORT2
DSP1
PORT2
DSP1
9
8
U7D
74LVC07ANS
U7D
74LVC07ANS
R27
330
R27
330
R37
10k
R37
10k
R25
330
R25
330
R33
10k
R33
10k
1
2
3
4
5
6
7
8
9
10
PORT3
CTRL
PORT3
CTRL
K
A
D2
HSU119
D2
HSU119
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