ASAHI KASEI

[AKD4589-B]

2005/07

FEATURE

AKD4589-B is an evaluation board for AK4589, a single chip 24bit CODEC that has two channels of ADC
and eight channels of DAC with internal DIR, DIT. It has interfaces with evaluation boards for A/D
converter and D/A converter of AKM's and make easy to evaluate AK4589. It also has the digital audio
interface and can achieve the interface with digital audio systems via opt-connector or BNC connector.

Ordering guide

AKD4589-B --- AK4589 Evaluation Board

10 wire flat cable for connection with printer port of PC (IBM-AT compatible
machine),control software for AK4589,driver for control software on Windows
2000/XP are apacked with this.

Control software does not support to I

C control, and does not work on Windows NT

Windows 2000/XP needs an installation of driver.
Windows 95/98/ME does not need an installation of driver.

FUNCTION

On-board clock generator
Compatible with 2 types of interface

- Optical output/input and BNC input
- Direct interface with AC3 decoder by 10pin header

10pin header for serial control interface

Input

Buffer

LIN

RIN

LOUT1

ROUT1

LOUT2

ROUT2

LOUT3

ROUT3

GND

AK4589

10pin Header

Control Data

BNC In

Opt In

Opt Out

AC3

-12V +12V

Output

Buffer

Regulator

BNC Out

Through Out

LOUT4

ROUT4

10pin Header

B, C, U, V

Figure 1. AKD4589-B Block Diagram

* Circuit diagram and PCB layout are attached at the end of this manual.

AK4589 Evaluation Board Rev.2

AKD4589-B

ASAHI KASEI

[AKD4589-B]

2005/07

EVALUATION BOARD MANUAL

Operation sequence

1) Set up the power supply lines. (See "Other jumpers set-up".)

Name

Color

Voltage

Used for

Comment and attention

+12V Red +12

+15V Regulator ,I/OBuffer(Op-amp)

Power supply for Regulator,I/OBuffer(Op-amp).
It should be always connected.

-12V Blue -12

-15V

I/O Buffer(Op-amp)

Power supply for I/OBuffer(Op-amp).
It should be always connected.

AGND

Black

Analog Ground

Analog Ground. It should be always connected.

DGND Black

Digital

Ground

Digital Ground. It should be connected when JP1
is open. This connector can be open when JP1 is
short.

Table 1. Set up of power supply lines

(Note)Each supply line should be distributed from the power supply unit.

2) Set-up of evaluation modes, jumper pins and DIP switches. (See the followings.)

3) Power on

AK4589 should be reset once after power-on of AKD4589-B.
Set SW1 (PDN) "L" once for power down of AK4589 after power-on of AKD4589-B.
And then set SW1 (PDN) "H".

ASAHI KASEI

[AKD4589-B]

2005/07

Evaluation mode

Applicable evaluation modes

(A) Evaluation of DAC part used internal DIR of AK4589 (See the followings)
(B) Evaluation of ADC part used internal DIT of AK4589 (See the followings)

(A) Evaluation of DAC part used internal DIR of AK4589

1-1. About digital inputs (bi-phase inputs)

1-1-1. Optical connector PORT3 (TORX176,RX0) or BNC connector J12(RX0) are used for digital

inputs(bi-phase inputs) .

1-1-2. Select Optical connector PORT3 (TORX176,RX0) or BNC Connector J12(RX0) for digital inputs

(bi-phase inputs) by JP3 (RX0)

Set JP3(RX0) "OPT" side when Optical connector PORT3(TORX176,RX0) is used for RX0 on

AKD4589-B.

Set JP3(RX0) "BNC" side when BNC connector J12(RX0) is used for RX0 on AKD4589-B.
(See Figure 2)

BNC

JP3

RX0

OPT

BNC

JP3

RX0

OPT

Using Optical connector

Using BNC

Figure 2. Setting of JP3(RX0) Selection of digital input (bi-phase input)

1-1-3. Write (0,0) into (D5:CM1,D4:CM0) of addr00H:CLK & Power Down Control of control registers of

AK4589 (DIR/DIT) part (CM10=00:Clock Mode=PLL Mode.)

Then clock source is PLL.

(Default setting is PLL. Able to evaluate AK4589 on default setting.)

1-1-4. Set DIP-Switch SW2-2 (MASTER) ON.

Then mode is master mode.
Audio Digital Interface Format is 24bit left justified.

(Please refer to datasheet.).
(Default setting is master mode. Able to evaluate AK4589 on default setting.)

1-2. About analog outputs

1-2-1. BNC connector J2 (LOUT1), J1 (ROUT1), J4 (LOUT2), J3 (ROUT3), J6 (LOUT3), J5 (ROUT3),

J8 (LOUT), J7 (ROUT4) are used for analog outputs.

ASAHI KASEI

[AKD4589-B]

2005/07

(B) ADC Evaluation of using internal DIT of AK4589

2-1. About analog inputs

2-1-1. BNC connectors J10 (LIN),J9 (RIN) are used for analog inputs.

2-2. About digital outputs (bi-phase outputs)

2-2-1. Optical connector PORT2 (TOTX176,TX1) or BNC connector J11 (TX1) are used for digital outputs.

2-2-2. .Select Optical connector PORT2 (TOTX176,TX1) or BNC Connecter J11 (TX1) for digital outputs

(bi-phase outputs) by JP2 (TX1)

Set JP2 (TX1) "OPT" side when Optical connector PORT2(TOTX176,TX1) is used for TX1 on
AKD4589-B.
Set JP2 (TX1) "BNC" side when BNC connector J11(TX1) is used for TX1 on AKD4589-B.
(See Figure3.)

BNC

JP2

TX1

OPT

BNC

JP2

TX1

OPT

Using Optical connector

Using BNC

Figure 3. Setting of JP2(TX1) Selection of digital output (bi-phase output)

2-2-3. Write (0,1) into (D5:CM1,D4:CM0) of addr00H:CLK & Power Down Control of control registers of

AK4589 (DIR/DIT) part (CM10=01:Clock Mode=X'tal Mode.)
Then clock source is X'tal (X1).

2-2-4. Set DIP-Switch SW2-2 (MASTER) ON.

Then mode is master mode.
Audio Digital Interface Format is 24bit left justified.

(Please refer to datasheet.).
(Default setting is master mode. Able to evaluate AK4589 on default setting.)

ASAHI KASEI

[AKD4589-B]

2005/07

Setting of DIP-Switch

[SW2]: Setting of AK4589 (SW2:No.2~6 is ON: 1(H), OFF:0(L))

No. Pin

OFF

Default

1 -

OFF

MASTER

Slave Mode

Master Mode

ON(1,H)

3 XTL1

ON(1,H)

4 XTL0

Detection of Sampling frequency (Refer Table 4,5)

ON(1,H)

5 CAD1

Setting of Chip Address (ADC/DAC PART)

OFF(0,L)

6 CAD0

Setting of Chip Address (ADC/DAC PART)

ON(1,H)

Table 2. Setting of SW2

(Note) Chip Address of ADC/DAC is fixed,CAD1,CAD0 is 0(L),1(H). (CAD10=01)
Therefore

setting

CAD1,CAD0

fixed, CAD1,CAD0 is OFF(0,L),ON(1,H).

Sampling frequency as follows

AK4589 has two methods for detecting the sampling frequency. Clock is compared between recovered clock and X'tal
oscillator by XTL1-0. This information outputs FS0, FS1, and FS2, FS3 bit for detecting the sampling frequency.
The compared X'tal frequency is selected by setting of XTL1-0 (Refer Table 4.) When XTL1-0 is ON(1,H),ON(1,H),
X'tal oscillator is stopped and the encored sampling frequency information of channel status output FS0, FS1, FS2, FS3,
PEM bit of resister control.

XTL1 XTL0 X'tal

Frequency

OFF(0,L) OFF(0,L)

11.2896MHz

OFF(0,L) ON(1,H)

12.288MHz

ON(1,H) OFF(0,L)

24.576MHz

ON(1,H)

(use channel status)

Default

Table 3. Reference X'tal frequency

Except XTL1,0= "1,1"

XTL1, 0= "1,1"

Consumer

mode

(Note 2)

Professional mode

FS3 FS2 FS1 FS0

Clock comparison

(Note 1)

Byte3

Bit3, 2,1,0

Byte0 Bit7,

Byte4 Bit6,

5,4,3

44.1kHz

0 0 0 0

0 1

0 0 0 0

0 0 0 1 Reserved

Reserved

(Others)

48kHz

0 0 1 0

1 0

0 0 0 0

32kHz

0 0 1 1

1 1

0 0 0 0

88.2kHz

( 1 0 0 0 )

0 0

1 0 1 0

96kHz

( 1 0 1 0 )

0 0

0 0 1 0

176.4kHz

( 1 1 0 0 )

0 0

1 0 1 1

192kHz

( 1 1 1 0 )

0 0

0 0 1 1

Note1: At least

�3% range is identified as the value in the Table 4. In case of intermediate frequency of those two, FS3-0

bits indicate nearer value. When the frequency is much bigger than 192kHz or much smaller than 32kHz, FS3-0
bits may indicate "0001".

Note2: When consumer mode, Byte3 Bit3-0 are copied to FS3-0 bits.

Table 4. Sampling frequency information

Электронный компонент: AKD4589