ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
-
1
-
GENERAL DESCRIPTION
The AK4537 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo
CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4537 is available in a
52-QFN, utilizing less board space than competitive offerings.
FEATURES
1. Resolution : 16bits
2. Recording Function
Stereo Mic Input
Stereo Line Input
1
st
MIC Amplifier : +20dB or 0dB
2
nd
Amplifier with ALC
+27.5dB
-8dB, 0.5dB Step (MIC input)
+12dB
-23.5dB, 0.5dB Step (LINE input)
ADC Performance : S/(N+D) : 79dB, DR, S/N : 83dB (MIC input)
S/(N+D) : 88dB, DR, S/N : 91dB (LINE input)
3. Playback Function
Digital De-emphasis Filter (tc=50/15
s, fs=32kHz, 44.1kHz, 48kHz)
Digital Volume (0dB
-127dB, 0.5dB Step, Mute)
Stereo Headphone-Amp
- S/(N+D) : 70dB, S/N : 90dB
- Output Power : 15mW@16
(HVDD=3.3V)
- Click Noise Free at Power ON/OFF
Mono Speaker-Amp with ALC
- S/(N+D) : 64dB@150mW, S/N : 90dB
- BTL Output
- Output Power : 400mW@8
(BEEP Input, HVDD=3.3V)
300mW@8
(MIN Input, ALC2=OFF, HVDD=3.3V)
Mono and Stereo Beep Inputs
Mono Line Output
- Differential Output
- Performance : S/(N+D) : 89dB, S/N : 95dB
Stereo Line Output
- Performance : S/(N+D) : 88dB, S/N : 92dB
4. Power Management
5. Master Clock
(1) PLL Mode
Frequencies : 11.2896MHz, 12MHz and 12.288MHz
Input Level : CMOS
(2) External Clock Mode
Frequencies : 2.048MHz
12.288MHz
6. Output Master Clock Frequencies : 32fs/64fs/128fs/256fs
7. Sampling Rate :
(1) PLL mode
8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
(2) External Clock mode
8kHz
48kHz
8. Control mode: 4-wire Serial / I
2
C Bus
9. Master/Slave mode
16-Bit
Stereo CODEC with MIC/HP/SPK-AMP
AK4537
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
-
2
-
10. Audio Interface Format : MSB First, 2's compliment
ADC : I
2
S, 16bit MSB justified
DAC : I
2
S, 16bit MSB justified, 16bit LSB justified
11. Ta = -10
70
C
12. Power Supply: 2.4V
3.6V (typ. 3.3V)
13. Power Supply Current
AVDD+DVDD : 19mA
PVDD : 1.2mA
HVDD (HP-AMP=ON, SPK-AMP=OFF) : 4mA
HVDD (HP-AMP=OFF, SPK-AMP=ON) : 7mA
12. Package : 52pin QFN (AK4534 pin compatible)
Block Diagram
ALC1
(IPGA)
AVDD
AVSS
MICOUTL
LIN1
LRCK
BICK
SDTO
SDTI
PDN
DSP
and
uP
DVDD
DVSS
HVDD
HVSS
VCOM
MUTET
ALC2
MOUT-
HPL
PMHPL
HP-AMP
HPR
PMHPR
HP-AMP
Control
Register
Interface
Audio
PMSPK
SPK-
AMP
SPP
SPN
I2C
CSN/CAD1
CCLK/SCL
CDTI/SDA
CDTO
PMMO
CAD0
MOUT+
XTI/MCKI
XTO
MCKO
VCOC
PVDD
PVSS
MIX
MIX
MIX
MPE
MIC Power
Supply
EXT/MICR
INT/MICL
MIC-AMP
0dB or 20dB
MPI
MIC Power
Supply
M/S
HPF
ADC
PMDAC
DATT
SMUTE
DAC
MIN
MOUT2
MIX
PLL
PMPLL
PMXTL
BEEPL
BEEPR
PMBPS
BEEPM
PMBPM
LIN2
ALC1
(IPGA)
RIN1
LOUT
ROUT
RIN2
MIC-AMP
0dB or 20dB
MICOUTR
PMMICR
ATT
PMLO
ATT
ATT
PMMICL
PMMICR or PMIPGR
PMMICL or PMIPGL
PMADL or PMADR
MIX
MIX
PMMIX
MIX
MIX
MIX
PMMICL
Figure 1. Block Diagram
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
-
3
-
Ordering Guide
AK4537VN
-10 +70C
52pin
QFN
(0.4mm
pitch)
AKD4537
Evaluation
board
for
AK4537
Pin Layout
EXT/MICR
RI
N1
52 51
1
50 49 48 47 46 45 44 43 42
39
38
37
36
35
34
33
32
31
30
29
24
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
11
AK4537VN
Top View
MPE
MPI
INT/MICL
VCOM
AVSS
AVDD
PVDD
PVSS
CCL
K/
SCL
DVDD
DVSS
XTO
XTI/MCKI
M/S
SPP
SPN
HVDD
HVSS
HPR
HPL
BEEPL
BEEPR
BEEPM
LI
N
2
RI
N2
MOU
T
+
MOU
T
-
LO
U
T
MOU
T
2
12
VCOC
25
28
NC
41
MI
N
CSN
/
CAD1
PDN
CDT
I
/
SDA
CDT
O
I2
C
SDT
I
SDT
O
LR
C
K
BI
CK
MC
K
O
NC
13
26
27
40
NC
ROUT
LI
N
1
CAD0
MUTET
MICOUTL
MICOUTR
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
-
4
-
Comparison with AK4534
1. Function
Function AK4534
AK4537
Line Input
No
Yes (Stereo)
Mic Input
Mono
Stereo
IPGA Mono
Stereo
Stereo Line Output
No
Yes
SPK-Amp Gain Select
No
Yes
MOUT Gain Select
No
Yes
Path from IPGA Lch to Analog
Output
No Yes
2. Pin
pin# AK4534 AK4537
1 MICOUT
MICOUTL
2 TST1 MICOUTR
3 EXT EXT/MICR
6 INT
INT/MICL
42 TST2 ROUT
43 TST3 LOUT
46 TST4 RIN2
47 TST5 LIN2
51 AIN
LIN1
52 NC
RIN1
3. Register
Addr Contents
00H
PMIPGL (IPGA Lch Power Control) is added.
PMLO (Stereo Line Output Power Control) is added.
01H
SPKG (SPK-Amp Output Power Select) is added.
02H
MOGN (MOUT Gain Select) is added.
MICM (IPGA Lch
MOUT) is added
03H
PSLO (Stereo Line Output Power Save Mode Select) is added.
MICL (IPGA Lch
LOUT/ROUT, HP-Amp, SPK-Amp) is added.
05H
HPLM, HPRM (HP-Amp Mono Output Select) is deleted.
HPM (HP-Amp Mono Output Select) is added.
07H
IPGAC (IPGA Control) is added.
0EH
ATTM (IPGA Lch
MOUT ATT Select) is added.
ATTS2-0 (IPGA Lch
LOUT/ROUT, HP-Amp, SPK-Amp ATT Select) is added.
0FH
IPGAR6-0 (Rch IPGA Control) is added.
10H
PMADR (ADC Rch Power Control) is added.
PMMICR (MIC-amp Rch Power Control) is added.
PMIPGR (IPGA Rch Power Control) is added.
INL (IPGA Lch Input Select) is added.
INR (IPGA Rch Input Select) is added.
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
-
5
-
PIN/FUNCTION
No. Pin
Name
I/O
Function
1
MICOUTL
O
MIC-Amp Lch Output Pin
2
MICOUTR
O
MIC-Amp Rch Output Pin
EXT
I
External Microphone Input Pin (Mono Input)
(PMMICR bit = "0")
3
MICR
I
Stereo Microphone Rch Input Pin
(PMMICR bit = "1")
4
MPE
O
MIC Power Supply Pin for External Microphone / Stereo Microphone Rch
5
MPI
O
MIC Power Supply Pin for Internal Microphone / Stereo Microphone Lch
EXT
I
Internal Microphone Input Pin (Mono Input)
(PMMICL bit = "0")
6
MICR
I
Stereo Microphone Lch Input Pin
(PMMICL bit = "1")
7 VCOM
O
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
8
AVSS
-
Analog Ground Pin
9
AVDD
-
Analog Power Supply Pin
10 PVDD
-
PLL Power Supply Pin
11 PVSS
- PLL
Ground
Pin
12 VCOC
O
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to PVSS with one resistor and capacitor in series.
13 NC
-
No Connect.
This pin should be left floating.
14 CAD0
I
Chip Address 0 Select Pin
15 PDN
I
Power-Down Mode Pin
"H": Power up, "L": Power down reset and initializes the control register.
CSN
I
Chip Select Pin (I2C = "L")
16
CAD1
I
Chip Address 1 Select Pin (I2C = "H")
CCLK
I
Control Data Clock Pin (I2C = "L")
17
SCL
I
Control Data Clock Pin (I2C = "H")
CDTI
I
Control Data Input Pin (I2C = "L")
18
SDA
I/O Control Data Input Pin (I2C = "H")
19 CDTO
O
Control Data Output Pin (I2C = "L")
20 I2C
I
Control Mode Select Pin
"H": I
2
C Bus, "L": 4-wire Serial
21 SDTI
I
Audio Serial Data Input Pin
22 SDTO
O
Audio Serial Data Output Pin
23 LRCK
I/O Input / Output Channel Clock Pin
24 BICK
I/O Audio Serial Data Clock Pin
25 MCKO
O
Master Clock Output Pin
26 NC
-
No Connect.
This pin should be left floating.
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