The AHA Galaxy TPC core technology is covered under multiple patents pending.
comtech aha corporation
comtech aha corporation
PRODUCT BRIEF
Galaxy TPC Cores
TURBO PRODUCT CODE ENCODER/DECODER CORES
Galaxy is a core generator for Turbo Product
Code (TPC) decoders. The generator was developed
to support a broad range of forward error correction
(FEC) code applications.
With input parameters set to support the
designer's system requirements, a custom TPC core
is generated. Since the core is customized for the
target application, only necessary features are
generated resulting in the most cost-effective TPC
solution. Comtech AHA Corporation (AHA)
delivers this core as a VHDL or Verilog netlist for
integration into an ASIC.
TPC PERFORMANCE
Turbo product codes have demonstrated
superior bit-error-rate performance over many FEC
solutions. Figure 1 shows the Bit Error Rate
performance of several TPCs with QAM
modulation. The TPC generator allows these
parameters as well as parameters effecting data rate
and block size to be independently adjusted to
achieve optimal performance.
Figure 1:
Code Performance Comparison
FEATURES
TPC technology is proven in silicon by
AHA4501, AHA4524, AHA4540, and AHA4541
Fully synchronous, one clock, one edge design
Configurable core allows trade-offs between error
rate performance, data rate and gate count
Supports data rates to greater than 1Gbits/sec
Supports block sizes up to 64 Kbits
Code rates range from 0.25 to 0.98
Supports many extended Hamming and parity
codes in 2 dimensional and higher configurations
Latency is guaranteed to be less than two blocks
Input quantization up to 8 bits
Programmable iterations up to 256 per block
Internal buffering allows flexible data interface
RAM interfaces support synchronous or
asynchronous designs
JTAG controller to support system-level debug
Production test through dedicated scan chains or
JTAG controller
Figure 2:
Various TPC Codes vs. Capacity
64QAM_2
V a r i o u s G a l a x y
T P C s o l u t i o n s
comtech aha corporation
Figure 3:
Turbo Product Code Core
FUNCTIONAL DESCRIPTION
The TPC core operates as a flow-through
device in a data path architecture. The input and
output data flow is controlled with synchronous
handshaking for each transfer. Internal buffering
provides flexibility in the input and output data
transfer rates. Data transfers can either be a
continuous stream on intermittent bursts or a
combination of the two.
The TPC core incorporates block
synchronization features on the input and output
data ports. The input port accepts block boundary
information on the SYNCI input signal. In
addition, the input port signals to the up-stream
module the block boundary location on the
SYNCIO output signal. The block boundaries on
the output of the TPC core is indicated to down-
stream module with the SYNCO output signal.
Two levels of configuration are available in
each core. The first level is performed before
delivery when the core is built. This level
customizes the core to the specific application and
assures the most cost-effective TPC solution. The
second level of configuration is done at run-time.
This allows the core's performance to change as the
system requirements change. For example as a
communication channel deteriorates or the QoS
(quality of service) requirement increases, the
number of decoding iterations can be increased.
Run-time configuration can either be done through
the JTAG port or directly on the CONFIG bus.
The primary purpose for the JTAG port is to
provide complete access to the TPC core when it is
embedded in a system-on-chip application. This is
not only necessary for complete fault coverage of
the core but also provides considerable flexibility in
system debug.
DELIVERABLES
The deliverables from AHA for a TPC core
include:
TPC core behavioral model - C/C++ model for
TPC Decoder. The API for the model is
customized for easy integration into a system
simulation. Delivered as a compiled object for
WindowsNT.
Hardware design - VHDL and/or Verilog netlist.
Customized for target memory library and
optimized to target gate library.
Verification vectors - complete verification suite
for the core. The suite achieves greater than 95%
fault coverage.
Test Bench - VHDL and/or Verilog test bench that
presents the verification vectors to the TPC core
and confirms proper operation.
Bus-functional model - VHDL and/or Verilog
model that emulates the communication protocol
on all TPC core interfaces.
A TPC encoder is also available from AHA.
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TPC Decoder Engine
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Input Data Storage
Dual Port RAM
(2 x input block size)
Intermediate Storage
Dual Port RAM
(1x or 2x block size)
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Output Data Storage
Dual Port RAM
(2 x block size)
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comtech aha corporation
PBgalaxy_0306
2006 Comtech AHA Corp.
comtech aha corporation
1126 Alturas Drive
fax: 208.892.5601
tel: 208.892.5600
e-mail: sales@aha.com
www.aha.com
Moscow, ID 83843-8331
A subsidiary of Comtech Telecommunications Corporation
ABOUT AHA
Comtech AHA Corporation (AHA) develops
and markets superior integrated circuits, boards,
and intellectual property core technology for
communications systems architects worldwide.
AHA has been setting the standard in Forward
Error Correction and Lossless Data Compression
technology for many years and provides flexible,
cost-effective solutions for today's growing
bandwidth and reliability challenges. Comtech
AHA Corporation is a wholly owned subsidiary of
Comtech Telecommuncations Corp. (NASDAQ:
CMTL). For more information, visit www.aha.com.
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