comtech aha corporation
This product is covered under multiple patents held or licensed by Comtech AHA
Corp.
This product is covered by a Turbo Code Patent License from France Telecom -
TDF - Groupe des ecoles des telecommunications.
*Request the AHA4501 Product Specification for complete details
comtech aha corporation
PRODUCT BRIEF*
AHA4501
36 MBITS/SEC TURBO PRODUCT CODE
ENCODER/DECODER
The AHA4501 is a single-chip Forward Error
Correction LSI device using Turbo Product Codes
(TPC). The device operates as a block code encoder
at the input or a block code decoder at the output of
a communication channel. Figure 1 shows a
functional block diagram of the device. Turbo
Product Codes offer a higher performance
alternative to Reed-Solomon or Reed-Solomon
concatenated with Viterbi error correction methods.
When encoding, a block of data is input into the
device's internal RAM. The device then calculates
error correction (ECC) and parity bits across each
dimension of the block, appends the ECC and parity
bits to the block, and then outputs the encoded
block.
When decoding, the device accepts soft
decision values and stores the data as a block in its
internal RAM. The block is then decoded
iteratively by running the block through the device's
soft in/soft out (SISO) decoder. The device iterates
a block to the maximum programmed iteration
limit. The decoded block is then output through the
device output data port.
Configuration, control and status of the device
is accomplished through read/writable registers via
a standard microprocessor interface. The device
also has an interrupt output signal.
FEATURES
PERFORMANCE:
Maximum 50 Mbits/second data rate encoding
and up to 36 Mbits/second data rate decoding with
a 50 MHz clock
Two or more devices can be used in parallel to
increase throughput
Optional "helical" interleaving (encoding) and
deinterleaving (decoding)
FLEXIBILITY:
Internal buffering allows continuous data
streaming
Programmable block size from 256 to 4096 bits
Two or three dimensional blocks
Programmable number of iterations per block up
to 32
Programmable quantization up to 6-bits for soft or
hard decision input data (decoding)
Support for external synchronization
SYSTEM INTERFACE:
Serial or 8-bit parallel input and output data ports
Selectable microprocessor interface for Intel or
Motorola processors
Control Commands for: Decode, Encode, Soft
Reset, Resynchronize and Dump Current Block
System Interrupts include Block Decode
Complete, Block Correction Incomplete, Sync
Mark Mismatch
Number of corrections per block accumulated in
an internal register
OTHERS:
3.3 Volt operation
100 pin quad flat package
Output signals may be tristated to facilitate board
level testing
Commercial or industrial temperature rating
APPLICATIONS
Various communication systems including, but
not limited to:
Wireless
Satellite
Networking
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MA
LE
MC
SN
GN
D
MA
[0
]
VD
D
GN
D
MA
[1
]
MA
[2
]
VD
D
NC
GN
D
M
I
NT
N_
INT
R
MR
D
Y
_D
T
A
C
K
N
NC
MD
A
T
A
[
7
]
MD
A
T
A
[
6
]
VD
D
GN
D
MD
A
T
A
[
5
]
MD
A
T
A
[
4
]
MD
A
T
A
[
3
]
MD
A
T
A
[
2
]
VD
D
GN
D
MD
A
T
A
[
1
]
MD
A
T
A
[
0
]
NC
NC
NC
NC
GN
D
ID
A
T
A
[
5]
ID
A
T
A
[
4]
ID
A
T
A
[
3]
VD
D
VD
D
GN
D
ID
A
T
A
[
2]
GN
D
ID
A
T
A
[
1]
ID
A
T
A
[
0]
OAC
P
T
IRD
Y
ISY
N
C
CLO
C
K
VD
D
VD
D
GN
D
GN
D
NC
NC
IA
CP
T
OS
YN
C
OR
D
Y
GN
D
VD
D
OD
A
T
A
[
7]
OD
A
T
A
[
6]
NC
GN
D
VDD
ODATA[5]
ODATA[4]
GND
VDD
ODATA[3]
ODATA[2]
ODATA[1]
VDD
GND
ODATA[0]
NC
NC
GND
VDD
NC
NC
NC
GND
VDD
IDATA[6]
IDATA[7]
NC
VDD
NC
GND
NC
NC
NC
VDD
GND
MUXMODE
TESTMODE
RESETN
MRDN_DSN
MWRN_RWN
GND
TRI_STATE
VDD
PROCMODE
AHA4501A-050 PQC
YYWWD - COUNTRY OF ORIGIN
LLLLL
comtech aha corporation
Figure 1:
AHA4501 Block Diagram
FUNCTIONAL OVERVIEW
ERROR CORRECTION CAPABILITY
The AHA4501 provides various levels of error
correction based on programmable parameters
including, block size, iterations executed on each
block and the number of quantization bits. Higher
numbers of iterations provide greater error correction
capability at the expense of lower data throughput.
AHA4501 block sizes range from 256 to 4096
bits and can be configured as a 2D or 3D array. The
device also supports several block types within each
block size, each with different code rates.
Throughput latency depends on the block size.
Table 1 gives a partial list of the code types
supported, including overall code block size and
data size in bits. Since Turbo Product Codes are
block codes, they can be shortened to achieve
virtually any block size and rate below those shown
in the table. Shortening of the codes must be done in
external hardware
The number of input quantization bits can be
varied from 1 to 6 bits when decoding. More
quantization bits provide better error correction
capability at the expense of greater complexity in
the system front end.
ENCODING
When encoding, data is input either serially or
in 8-bit parallel using a fully synchronous
ready/accept handshake protocol. Data input to the
device is stored in the Original Array (OA) SRAM
as either a 2D block consisting of k
1
k
2
bits or a 3D
block consisting of k
1
k
2
k
3
bits. Each dimension
length of a block can be different and can range
from 4 to 64 bits.
After an entire block is loaded, the device
calculates a number of ECC bits and one parity bit
for each of the rows and columns of the block and
appends them to their respective rows and columns.
This brings the total number of bits in a 2D block to
n
1
n
2
. For example, a 2D block built from k
1
k
2
input bits is modified into a block of n
1
n
2
bits. The
common notation for such a block is (n
1
,k
1
) x (n
2
,k
2
).
The encoded block is then output from the Hard
Decision Array (HDA) SRAM serially on ODATA[0].
DECODING
When decoding, the device accepts 1 to 6 bit
quantization soft values from an A to D converter
and stores the values in OA SRAM as either a 2D
block consisting of n
1
n
2
values or as a 3D block
consisting of n
1
n
2
n
3
values.
Decoding is done by iteratively passing a block
through the SISO decoder a number of times until
there are no errors to correct or until a
predetermined number of iterations has been
completed. One iteration of a block requires that all
n
1
and n
2
axes (2D) or all n
1
, n
2
and n
3
axes (3D) be
passed through the SISO decoder. Intermediate data
generated by each iteration is stored in the
Intermediate Storage Array (ISA) SRAM.
When the device has completed iterating, the
block is output from the HDA SRAM either serially
on ODATA[0] or in parallel on ODATA[7:0] using a
fully synchronous ready/accept handshake protocol.
The decoder data rate is dependent on the code
type and the number of iterations. Table 2 gives
approximate data rates at different iterations. Note
that multiple devices may be run in parallel with
minimal external logic to achieve higher data rates.
IDATA[7:0]
SISO
INPUT
ISA
OUTPUT
ODATA[7:0]
ORDY
OACPT
OSYNC
ENCODER/
HDA
SRAM
FEEDBACK
MULTIPLIER
OA
SRAM
CONTROL REGISTERS
SRAM
MICROPROCESSOR
INTERFACE
MU
XMO
D
E
MD
A
T
A[7:0]
PR
O
C
MODE
MC
SN
MA
[2:0]
MR
DN
_D
SN
MWR
N
_
R
WN
MA
LE
M
I
NTN_INTR
IRDY
IACPT
ISYNC
CLOCK
CLO
C
K
RESETN
AHA4501
DECODER
MR
D
Y
_
D
T
A
C
K
N
comtech aha corporation
Table 1:
Code Types Supported by AHA4501
Table 2:
Data Rates* at Different Iterations
*
Reflects coded rate which includes error correction
bits.
** Max rate for fastest codes.
Figure 2:
Turbo Product Code vs. Reed-Solomon/Viterbi Performance Comparison
Figure 3:
Comparison of TPC Code Types
BLOCK SIZE
(bits)
DATA
SIZE
RATE
CODE
STRUCTURE
4096
3249
0.793
2D
4096
2028
0.495
3D
4096
1331
0.325
3D
2048
1482
0.724
2D
2048
858
0.419
3D
1024
676
0.660
2D
1024
363
0.354
3D
512
286
0.559
2D
256
121
0.473
2D
ITERATIONS DATA RATE
(Mbits/sec)**
2D
3D
2
36
25
3
25
18
4
19
14
6
13
9
12
7
4.9
32
2.7
1.9
1
2
3
4
5
6
7
8
Eb/No (dB)
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
Bit Error Rate, P(e)
(64,57) x (64,57) Hamming Product Code, Rate = 0.793
Uncoded PSK, rate=1
RS/Viterbi, Rate=0.806
RS/Viterbi, Rate=0.790
TPC, 1 Iteration
2 Iterations
3 Iterations
4 Iterations
6 Iterations
32 Iterations
0
1
2
3
4
5
6
7
8
9
10
11
Eb/No (dB)
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
Bit Error Rate, P(e)
Hamming Product Code, Block Size 4096 bits
Uncoded PSK Channel
(64,57)x(64,57), rate=.793
(32,26)x(32,26)x(4,3), rate=.495
(16,11)x(16,11)x(16,11), rate=.325
1126 Alturas Drive
Moscow, ID 83843-8331
comtech aha corporation
PB4501_1203
2005 Comtech AHA Corp.
comtech aha corporation
fax: 208.892.5601
tel: 208.892.5600
e-mail: sales@aha.com
www.aha.com
A subsidiary of Comtech Telecommunications Corporation
comtech aha corporation
PERFORMANCE CURVES
Figure 2 shows a comparison between the error correction performance of the AHA4501 TPC and the
concatenated Reed-Solomon/Viterbi compared with uncoded Phase Shift Keying assuming a channel with
additive white Gaussian noise (AWGN). Note that the TPC implementation consistently outperforms
RS/Viterbi using only two iterations. Additional iterations increase performance.
Figure 3 compares different block codes each with a 4096 bit block size. Note that error correction
performance is increased by using block codes with lower code rates.
Figure 4:
Performance Curve for (64,56) x (64,57), rate = 0.793 Code
Figure 4 shows the E
b
/N
o
required to achieve a Bit Error Rate (BER) of 10
-5
with various numbers of
iterations and input quantization bits. Note that a very low E
b
/N
o
ratio can be obtained using only 3 bits of
quantization and 3 or 4 iterations per block.
ABOUT AHA
Comtech AHA Corporation (AHA) develops
and markets superior integrated circuits, boards,
and intellectual property core technology for
communications systems architects worldwide.
AHA has been setting the standard in Forward Error
Correction and Lossless Data Compression
technology for many years and provides flexible,
cost-effective solutions for today's growing
bandwidth and reliability challenges. Comtech
AHA Corporation is a wholly owned subsidiary of
Comtech Telecommuncations Corp. (NASDAQ:
CMTL). For more information, visit www.aha.com.
ORDERING INFORMATION
32
16
12
8
6
5
4
3
2
1
6
5
4
3
2
1
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
E
b
/N
0
(
d
B)
f
o
r BE
R =
1
0
-
5
Iterations
Soft Input Bits
6-7
5-6
4.5-5
4-4.5
3.75-4
3.5-3.75
3.25-3.5
3-3.25
E
b
/N
0
PART NUMBER
DESCRIPTION
AHA4501A-050 PQC
36 Mbits/sec Turbo Product
Code Encoder/Decoder -
Commercial Temperature
AHA4501A-050 PQI
36 Mbits/sec Turbo Product
Code Encoder/Decoder -
Industrial Temperature
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