Agilent HDMP-2634
2.5/1.25 GBd Serdes Circuit
Data Sheet
Features
10-bit wide parallel Tx, Rx busses
125 MHz TBC and RBC[0:1]
Option to set Tx and Rx serial
data rates separately
Parallel data I/O, clocks and
control compatible with SSTL_2
Differential PECL or LVTTL REFCLK
at 125 MHz
Double data rate transfers
Source synchronous clocking of
transmit data
Source centered or source
synchronous clocking of
receive data
Dual or single receive byte
clocks
Parallel loopback mode
Differential BLL serial I/O with
on-chip source termination
14 mm, 64-pin MQFP package
Single +3.3 V power supply
Applications
Gigabit ethernet channel
aggregation trunks
Fast serial backplanes
Clusters
Ordering Information
Part Number
Parallel I/O
HDMP-2634
SSTL_2
Description
This data sheet describes the
HDMP-2634 Serdes device for
2.5 GBd serial data rates.
The HDMP-2634 Serdes is a silicon
bipolar integrated circuit in a metal-
lized QFP package. It provides a
low-cost physical layer solution for
2.5 GBd serial link interfaces includ-
ing a complete Serialize/Deserialize
(Serdes) function with transmit and
receive sections in a single device.
The HDMP-2634 is also capable of
operating on 1.25 GBd serial links.
Input pins TX_RATE and RX_RATE
select the data rates on the transmit
and receive sides, respectively.
As shown in Figure 1, the transmit-
ter section accepts 10-bit wide par-
allel SSTL_2 data (TX[0:9]) and a
125 MHz SSTL_2 byte clock (TBC)
and serializes them into a high-
speed serial stream. The parallel
data is expected to be "8B/10B"
encoded data or equivalent. At the
source, TX[0:9] and TBC switch
synchronously with respect to a 125
MHz clock internal to the sender.
New data are emitted on both edges
of TBC; this is called Double Data
Rate (DDR). The HDMP-2634 finds
a sampling window between the
two edges of TBC to latch TX[0:9]
data into the input register of the
transmitter section when
TX_RATE=1. If TX_RATE=0, the
user must ensure no data transi-
tions on the falling edge of TBC
and this edge is used to latch in
parallel data resulting in a 1.25
GBd serial stream.
The transmitter section's PLL
locks to the 125 MHz TBC. This
clock is then multiplied by 20 to
generate the 2500 MHz serial
clock for the high-speed serial
outputs. The high-speed outputs
are capable of interfacing directly
to copper cables or PCB traces
for electrical transmission or to
a separate fiber optic module
for optical transmission. The
high-speed outputs include user-
controllable skin-loss equalization
to improve performance when
driving copper lines.
The receiver section accepts a
serial electrical data stream at
1.25 or 2.5 GBd and recovers
10-bit wide parallel data. The
receiver PLL locks onto the incom-
ing serial signal and recovers the
2
high-speed incoming clock and
data. The serial data is converted
back into 10-bit parallel data,
optionally recognizing the first
seven bits of the K28.5+ comma
character to establish byte align-
ment. If K28.5+ detection is en-
abled, the receiver section is able
to detect comma characters at
1.25 GBd or 2.5 GBd depending
on the value of the RX_RATE pin.
The recovered parallel data is
presented at SSTL_2 compatible
outputs RX[0:9], along with a
pair of 125 MHz SSTL_2 clocks,
RBC[0] and RBC[1], that are 180
degrees out of phase from one
another and which represent the
remote clock. Rising edges of
RBC[0] and RBC[1] may be used
to latch RX[0:9] data at the desti-
nation. Alternatively, both edges
of either RBC[1] or RBC[0] may
be used to latch Rx data (DDR).
The preceding applies when
RX_RATE=1 and RBC_SYNC=0.
For short distances, there may be
a need to have ASICs communi-
cate directly using parallel Tx and
Rx lines without the serdes inter-
mediary. To enable this, the Tx
and Rx parallel timing schemes
must be symmetrical. When
RBC_SYNC=1 and RX_RATE=1
such symmetry is obtained. In
this mode, the RX[0:9] lines
switch simultaneously with the
rising and falling edges of
RBC[1] or RBC[0] just as the
TX[0:9] lines switch simulta-
neously with TBC.
If RX_RATE=0 and RBC_SYNC=1
then the RX[0:9] lines switch
with the rising edges of RBC[1]
just as the TX[0:9] lines switch
with the rising edges of TBC. If
RBC_SYNC=0 then RX[0:9] data
may be latched on the rising
edges of RBC[1] and RBC[0]. In
this latter mode, the RBC[0:1]
clocks operate at a 62.5 MHz rate.
In summary, by setting
RBC_SYNC=0 the timing of
transmit and receive parallel data
with respect to TBC and
RBC[0:1] may be arranged so
that the upstream protocol device
can generate and latch data very
simply. This is the source cen-
tered mode of operation (case A
and C in Table 1, page 8). Alter-
natively, setting RBC_SYNC=1
provides for timing symmetry
between Tx and Rx parallel lines
at both 1.25 GBd and 2.5 GBd
rates. This is the source synchro-
nous mode of opertion (case B
and D in Table 1, page 8).
Note when EN_CDET=1, the first
transition of byte 0 of a comma
will either coincide with the rising
edge of RBC[1] or precede it.
This applies regardless of the
RX_RATE setting.
Table 1 summarizes the behavior
of the Rx parallel section under
all values of RX_RATE and
RBC_SYNC. For test purposes,
the transceiver provides for
on-chip parallel to parallel local
loopback functionality controlled
through the EWRAP pin. Addi-
tionally, the byte alignment fea-
ture via detection of the first
seven bits of the K28.5+ charac-
ter may be disabled. This may be
useful in proprietary applications
which use alternative methods to
align the parallel data.
The HDMP-2634 accepts either a
differential PECL or a LVTTL
reference clock input at 125 MHz.
HDMP-2634 Block Diagram
The HDMP-2634 (Figure 2) is
designed to transmit and receive
10-bit wide parallel data over
high-speed serial communication
lines. The parallel data applied to
the transmitter is expected to be
encoded per the 8B/10B encod-
ing scheme with special reserved
characters for link management
purposes. Other encoding
schemes will also work as long as
they provide DC balance and a
sufficient number of transitions.
The HDMP-2634 incorporates the
following:
SSTL_2 Parallel I/O
High Speed Phase Locked
Loops
Parallel to Serial Converter
High Speed Serial Clock and
Data Recovery Circuitry
Comma Character Recognition
per Fibre Channel
Specifications
Byte Alignment Circuitry
Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit
wide single ended SSTL_2
parallel data at inputs TX[0:9].
The SSTL_2 TBC clock provided
by the sender of the transmit data
is used as the transmit byte clock.
The TX[0:9] and TBC signals
must be properly aligned as
shown in Figure 3. If
TX_RATE=1, TX[0:9] data are
latched between both edges of
TBC. If TX_RATE=0, TX[0:9]
data are latched on the falling
edge of TBC. The TX[0:9] and
TBC inputs are unterminated
SSTL_2 inputs per section 4.1 of
the SSTL_2 standard (Figure 11).
TX PLL/CLOCK GENERATOR
The Transmitter Phase Locked
Loop and Clock Generator block
is responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based
on the supplied transmit byte
clock (TBC). Incoming data must
be synchronous with TBC
(Figures 3a-3b). Use of TBC to
determine sampling points to
latch data obviates the need for
PLLs in the data source.
3
SO
TX PLL
CLOCK
GENERATOR
REFCLK[0:1]
TX_RATE
RX_RATE
RBC[0:1]
COM_DET
EN_CDET
OUTPUT
DRIVER
TX CLOCKS
INPUT
LATCH
RX[0:9]
TXCAP1
TXCAP0
TX[0:9]
RX CLOCKS
EWRAP
OUTPUT
SELECT
FRAME
MUX
RX PLL
CLOCK
RECOVERY
INPUT
SELECT
FRAME
DEMUX
AND
BYTE SYNC
INPUT
SAMPLER
REF_RATE
RBC_SYNC
SI
TBC
RXCAP0
RXCAP1
Figure 1. Typical application using HDMP-2634.
Figure 2. Block diagram of HDMP-2634.
HDMP-2634
ASIC
SO
RECEIVER SECTION
PLL
TRANSMITTER SECTION
COM_DET
REFCLK[0:1]
SI
PLL
RBC[0:1]
EN_CDET
RX_RATE
REF_RATE
RBC_SYNC
RX[0:9]
EWRAP
TX[0:9]
TBC
TX_RATE
4
FRAME MUX
The FRAME MUX accepts 10-bit
wide parallel data from the
INPUT LATCH. Using internally
generated high-speed clocks, this
parallel data is multiplexed into a
2.5 GBd serial data stream. The
data bits are transmitted sequen-
tially from TX[0] to TX[9]. The
leftmost bit of K28.5+ is on
TX[0].
OUTPUT SELECT
The OUTPUT SELECT block
picks the serial data to drive on
to the serial output line. In
normal operation, the serialized
TX[0:9] data is placed at SO
. In
parallel loopback (EWRAP=1)
mode, the SO
pins are held
static at logic 1 and the internal
serial output signal going to the
INPUT SELECT block of the
receiver section is used to gener-
ate RX[0:9]. In addition, the
OUTPUT SELECT block allows
the user to control the amount of
pre-emphasis used on the SO
pins. If pre-emphasis is used,
0
1 and 1
0 transitions on
SO
have greater amplitude than
0
0 and 1
1 transitions. This
increased amplitude is used to
offset the effects of skin loss and
dispersion on long PCB transmis-
sion lines. Pre-emphasis is con-
trolled by the EQAMP pin (Table
2 and Figure 9).
INPUT SELECT
The INPUT SELECT block picks
the serial data that will be
parallelized to drive RX[0:9]. In
normal operation, serial data is
accepted at SI
. In parallel
loopback (EWRAP=1) mode, the
internal serial output signal from
the OUTPUT SELECT block of
the transmitter section is used to
generate RX[0:9].
RX PLL/CLOCK RECOVERY
The Receiver Phase Locked Loop
and Clock Recovery block is re-
sponsible for frequency and
phase locking onto the incoming
serial data stream and recovering
the bit and byte clocks. An auto-
matic locking feature allows the
Rx PLL to lock onto the input
data stream without external PLL
training controls. It does this by
continually frequency locking
onto the 125 MHz reference
clock, and then phase locking
onto the selected input data
stream. An internal signal detec-
tion circuit monitors the presence
of the input and invokes the
phase detection as the data
stream appears. Once bit locked,
the receiver generates the high-
speed sampling clock for the
input sampler.
INPUT SAMPLER
The INPUT SAMPLER is respon-
sible for converting the serial
input signal into a retimed bit
stream. To accomplish this, it
uses the high-speed serial clock
generated from the RX PLL/
CLOCK RECOVERY block. This
serial bit stream is sent to the
FRAME DEMUX AND BYTE
SYNC block.
FRAME DEMUX AND BYTE SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high-speed serial bit
stream. This block is also
responsible for recognizing the
first seven bits of the K28.5+
positive disparity comma charac-
ter (0011111xxx). When recog-
nized, the FRAME DEMUX AND
BYTE SYNC block works with the
RX PLL/CLOCK RECOVERY
block to select the proper parallel
data edge out of the bit stream so
that the next comma character
starts at RX[0]. When a comma
character is detected and realign-
ment of the receive byte clock
RBC[0:1] is necessary, these
clocks are stretched (never sliv-
ered) to the next correct align-
ment position. RBC[0:1] will be
aligned by the start of the next
ordered set (two-byte group)
after K28.5+ is detected. The
start of the next ordered set will
be aligned with the rising edge of
RBC[1], independent of the
RX_RATE pin setting. Per the
Fibre Channel encoding scheme,
comma characters must not be
transmitted in consecutive bytes
so that the receive byte clocks
may maintain their proper recov-
ered frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
(RX[0:9]) properly aligned to the
receive byte clock (RBC[0:1]) as
shown in Figures 5a-5d and
Table 1. These output drivers
provide single ended SSTL_2
compatible signals.
RECEIVER LOSS OF SIGNAL
The RECEIVER LOSS OF SIGNAL
block examines the peak-to-peak
differential amplitude at the SI
input. When this amplitude is too
small, RX_LOS is set to 1, and
RX[0:9] are set to logic one
(1111111111). This prevents
generation of random data at
the RX[0:9] pins when the serial
input lines are disconnected.
When the signal at SI
is a valid
amplitude, RX_LOS is set to
logic 0, and the output of the
INPUT SELECT block is passed
through.
5
SSTL_2 COMPATIBILITY
The HDMP-2634 works with pro-
tocol (FC-1 or MAC) devices
whose VDDQ voltage is nominally
2.5 V. Note that the HDMP-2634
works with a single V
CC
supply of
3.3 V. Nonetheless, RX[0:9] and
RBC[0:1] generate output volt-
ages that are compatible with
section 4.1 of the SSTL_2 stan-
dard and are not meant to be
terminated in 50
. In addition,
the HDMP-2634 provides a
VREFR output pin which may be
used at the protocol IC in order
to differentially detect a high or a
low on RX[0:9]. Alternatively,
this voltage may be generated on
the PCB using a resistor divider
from VDDQ or V
CC
while ignoring
the VREFR output of the HDMP-
2634. The HDMP-2634 expects
SSTL_2 compatible signals at the
TX[0:9] and TBC pins. These
pins are unterminated per section
4.1 of the SSTL_2 standard
(Figure 11). The VREFT input
pin is used by the HDMP-2634 to
differentially detect a high or low
on TBC and TX[0:9]. VREFT may
be generated by the protocol
device or on the PCB using a
resistor divider from VDDQ or
V
CC
.
MULTI-RATE OPERATION
The HDMP-2630/2631 provide
hooks for initializing multi-rate
links. A possible algorithm oper-
ates as follows. In a point to point
link, each node sets its TX_RATE
input pin high to transmit at the
highest possible data rate. At the
same time, each node tries differ-
ent values of RX_RATE to see at
which data rate intelligible data is
received. Once this data rate is
found, TX_RATE is set to enable
this rate. For example, suppose a
node that is capable of operating
at 1.25 GBd and 2.5 GBd rates is
establishing a link with a node
that is capable of only 2.5 GBd.
Both nodes will start emitting at
2.5 GBd because this is their
highest rate. The first node will
try receiving at 1.25 GBd rate. It
will not succeed and will there-
fore try 2.5 GBd reception, which
will succeed. The second node is
set to 2.5 GBd and has been re-
ceiving correct data. These two
nodes will settle to 2.5 GBd.
If the second node in the example
above operated at 1.25 GBd only,
then the first node would see
intelligible 1.25 GBd data and set
its TX_RATE=0, at which time
the second node would also start
seeing intelligible data. These
nodes would settle to 1.25 GBd.
If both nodes are 1.25/2.5 GBd
capable, then they will settle to
2.5 GBd. With this algorithm,
nodes need not have a common
lowest common denominator data
rate to interoperate.
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