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Электронный компонент: HDMP-1022

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615
Low Cost Gigabit Rate
Transmit/Receive Chip Set with
TTL I/Os
Preliminary Technical Data
Features
Transparent, Extended
Ribbon Cable Replacement
Implemented in a Low Cost
Aluminum M-Quad 80
Package
High-Speed Serial Rate
150-1500 MBaud
Standard TTL Interface
16, 17, 20, or 21 Bits Wide
Reliable Monolithic Silicon
Bipolar Implementation
On-Chip Phase-Locked
Loops
- Transmit Clock Generation
- Receive Clock Extraction
Applications
Backplane/Bus Extender
Video, Image Acquisition
Point to Point Data Links
Implement SCI-FI Standard
Implement Serial HIPPI
Specification
data. Parallel data (a frame)
loaded into the Tx (transmitter)
chip is delivered to the Rx
(receiver) chip over a serial
channel, which can be either a
coaxial copper cable or optical
link.
The chip set hides from the user
all the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding.
Unlike other links, the phase-
locked-loop clock extraction
circuit also transparently provides
for frame synchronizationthe
user is not troubled with the
periodic insertion of frame syn-
chronization words. In addition,
the dc balance of the line code is
automatically maintained by the
chip set. Thus, the user can
transmit arbitrary data without
restriction. The Rx chip also
includes a state-machine con-
troller (SMC) that provides a
startup handshake protocol for
the duplex link configuration.
The serial data rate of the T/R link
is selectable in four ranges (see
tables on page 5), and extends
from 120 Mbits/s up to 1.25
Gbits/s. The parallel data interface
is 16 or 20 bit TTL, pin select-
able. A flag bit is available and
can be used as an extra 17th or
21st bit under the user's control.
The flag bit can also be used as an
even or odd frame indicator for
dual-frame transmission. If not
used, the link performs expanded
error detection.
The serial link is synchronous,
and both frame synchronization
and bit synchronization are main-
tained. When data is not available
to send, the link maintains
synchronization by transmitting
fill frames. Two (training) fill
frames are reserved for
handshaking during link startup.
User control space is also sup-
ported. If Control Available is
asserted at the Tx chip, the least
significant 14 or 18 bits of the
data are sent and the Rx Control
Available line will indicate the
data as a Control Word.
It is the intention of this data
sheet to provide the design
engineer all of the information
regarding the HDMP-1022/1024
chipset necessary to design this
product into their application. To
assist you in using this data sheet,
the following Table of Contents is
provided.
HDMP-1022 Transmitter
HDMP-1024 Receiver
Description
The HDMP-1022 transmitter and
the HDMP-1024 receiver are used
to build a high-speed data link for
point-to-point communication.
The monolithic silicon bipolar
transmitter chip and receiver chip
are each provided in a standard
aluminum M-Quad 80 package.
From the user's viewpoint, these
products can be thought of as
providing a "virtual ribbon cable"
interface for the transmission of
(5/97)
617
Typical Applications
The HDMP-1022/1024 chipset
was designed for ease of use and
flexibility. This allows the
customer to tailor the use of this
product, through the configura-
tion of the link, based on his
specific system requirements and
application needs. Typical
applications range from backplane
and bus extension to digital video
transmission.
Low latency bus extension of a 16
or 20 bit wide data bus may be
achieved using the standard
duplex configuration (see Figure
1d). In full duplex, the HDMP-
1022/1024 chipset handles all of
the issues of link startup, main-
tenance, and simple error
detection.
If the bus width is 32 or 40 bits
wide, the HDMP-1022/1024
chipset is capable of sending the
large data frame as two separate
frame segments, as shown in
Figure 1b. In this mode, called
Double Frame Mode, the FLAG
bit is used by the transmitter and
receiver to indicate the first or
second frame segment
(Figure 19). The HDMP-1022/
1024 chipset in Double Frame
Mode may also be configured in
full duplex to achieve a 32/40 bit
wide bus extension.
For digital video transmission,
simplex links are more common.
The HDMP-1022/1024 chipset
can transmit 16 to 21 bits of
parallel data in standard or
broadcast simplex mode.
Additionally, 32 to 40 bit wide
data can be transmitted over a
single line (in Double Frame
Mode) or two parallel lines, as in
Figure 1c.
Figure 1. Various Configurations Using the HDMP-1022/1024.
Tx
Rx
CLK
CLK
A) 16/20 BIT SIMPLEX TRANSMISSION
CLK
Tx
Rx
CLK
MUX
DEMUX
B) 32/40 BIT SIMPLEX TRANSMISSION
CLK
Tx
Rx
CLK
CLK
Tx
Rx
CLK
C) 32/40 BIT SIMPLEX TRANSMISSION
WITH HIGH CLOCK RATES
CLK
Tx
Rx
CLK
CLK
Rx
Tx
CLK
D) 16/20 BIT DUPLEX TRANSMISSION
CLK
Tx
Rx
CLK
E) SIMPLEX BROADCAST TRANSMISSION
Rx
CLK
Rx
CLK
618
For timing diagrams for the
standard configurations, see the
Appendix section entitled Link
Configuration Examples.
The HDMP-1022/1024 chipset
can support serial transmission
rates from 150 MBd to 1.5 GBd
for each of these configurations.
The chipset requires the user to
input the link data rate by assert-
ing DIV1 and DIV0 accordingly.
To determine the DIV1/DIV0
setting necessary for each
application, refer to the section:
Setting the Operating Data Rate
Range
below.
Setting the Operating
Data Rate Range
The HDMP-1022/1024 chipset
can operate from 150 MBaud to
1500 MBaud. It is divided into
four operating data ranges with
each range selected by setting
DIV1 and DIV0 as shown in the
tables on the following page.
The purpose of following example
is to help in understanding and
using these tables. This specific
example uses the table in Figure 3
entitled "Typical 20-bit Mode Data
Rates."
It is desired to transmit a 20 bit
parallel word operating at 55 MHz
(55 MWord/sec). Both the Tx and
Rx must be set to a range that
covers this word rate. According
to the table entitled "Typical
Operating Rates for 20 Bit Mode"
on the next page, a setting of
DIV1/DIV0 = logic `0/0' allows a
parallel input word rate of 29.2 to
62.5 MHz . This setting easily
accommodates the required 55
MHz word rate. The user serial
data rate can be calculated as:
Serial
20 bit
55 Mw
Data Rate
= () ()
word
sec
= 1100
MBits/sec
The baud rate includes an
additional 4 bits that G-LINK
transmits for link control and
error detection. The serial baud
rate is calculated as:
Serial
24 bits
55 Mw
Baud Rate
= () ()
word
sec
= 1320
MBaud
The 55 MHz example is one in
which the parallel word rate
provides only one possible DIV1/
DIV0 setting.
Some applications may have a
parallel word rate that seems to fit
two ranges. As an example, a 35
MHz (35 MWord/s) parallel data
rate falls within two ranges (DIV0/
DIV1 = 0/0 and DIV0/DIV1 = 0/
1) in 20 Bit Mode. Per the table, a
setting of DIV1/DIV0 = 0/1 gives
an upper rate of 37.5 MHz , while
a setting of DIV1/DIV0 = 0/0
gives a lower rate of 29.2 MHz.
These transition data rates are
stated in the tables as typical
values and may vary between
individual parts. Each transmitter/
receiver has continuous band
coverage across its entire 150 to
1500 MBaud range and has
overlap between ranges. Each
transmitter/receiver will permit a
35 MHz parallel data rate, but it is
suggested that DIV0 be a jumper
that can be set either to logic `1'
(open) or logic `0' (ground). This
allows the design to accommodate
both ranges for maximum flexibil-
ity. This technique is recom-
mended whenever operating near
the maximum and minimum of
two word rate ranges. The above
information also applies to the
HDMP-1022/1024 chipset when
operating in 16 bit mode.
PRE-RELEASE
PRODUCT DISCLAIMER
This product is in development at the
Hewlett-Packard CSSD in San Jose,
California. Until Hewlett-Packard
releases this product for general
sales, HP reserves the right to alter
specifications, features, capabilities,
functions, manufacturing release
dates, and even general availability of
the product at any time.
619
Figure 3. Typical 20 Bit Mode Data Rates.
Figure 2. Typical 16-bit Mode Data Rates.
HDMP-1022 (Tx), HDMP-1024 (Rx)
Typical Operating Rates for 16 Bit Mode
[1]
Tc = 0
C to +85
C, V
CC
= 4.5 V to 5.5 V
Parallel Word Rate
Serial Data Rate
Serial Baud Rate
(Mword/sec)
(Mbit/sec)
(MBaud)
DIV1
DIV0
Range
Range
Range
0
0
35
75 (max)
560
1200 (max)
700
1500 (max)
0
1
17.5
45
280
720
350
900
1
0
8.8
22.5
140
360
175
450
1
1
7.5 (min)
11.25
120 (min)
180
150 (min)
225
Notes:
1. All values are typical unless otherwise noted by (min) or (max).
2. All values in this table are expected for a BER less than 10
-14
.
HDMP-1022 (Tx), HDMP-1024 (Rx)
Typical Operating Rates for 20 Bit Mode
[1]
Tc = 0
C to +85
C, V
CC
= 4.5 V to 5.5 V
Parallel Word Rate
Serial Data Rate
Serial Baud Rate
(Mword/sec)
(Mbit/sec)
(MBaud/sec)
DIV1
DIV0
Range
Range
Range
0
0
29.2
62.5 (max)
583
1250 (max)
700
1500 (max)
0
1
14.6
37.5
292
750
350
900
1
0
7.3
18.8
146
375
175
450
1
1
6.3 (min)
9.4
125 (min)
187.5
150 (min)
225
Notes:
1. All values are typical unless otherwise noted by (min) or (max).
2. All values in this table are expected for a BER less than 10
-14
.
,,,,
,,
,,
0/0
0/1
1/0
1/1
5
25
50
75
100
125
2500
2000
1500
1000
500
100
790
380
190
110
320
640
1280
1800
DIV 1 / DIV 0
BAUD RATE = 20 x FRAME RATE
SERIAL DATA RATE (Mbaud)
FRAME RATE (Mwords/sec)
0/0
0/1
1/0
1/1
4
25
50
75
100
2500
2000
1500
1000
500
100
DIV 1 / DIV 0
BAUD RATE = 24 x FRAME RATE
SERIAL DATA RATE (Mbaud)
FRAME RATE (Mwords/sec)
,,,,
,,
790
380
190
110
320
640
1280
1800
620
the transmitter. The clock
generator section performs the
clock multiplication to the
necessary serial clock rate.
By setting EHCLKSEL high, the
user may provide an external high
speed serial clock at STRBIN.
This clock is used directly by the
high speed serial circuitry to
output the serial data.
Control Logic and C-Field
Encoder
The Control Logic is responsible
for determining what information
is serially sent to the output. If
CAV* is low, it sends the data at
D0..D8 and D9..D17 as control
word information. If CAV* is high
and DAV* is low, it sends parallel
word data at the data inputs. If
neither CAV* nor DAV* is set low,
then the transmitter assumes the
link is not being used. In this
state, the control logic triggers
the Data Encoder to send Fill
Frames to maintain the link DC
HDMP-1022 Tx Block
Diagram
The HDMP-1022 was designed to
accept 16 or 20 bit wide parallel
data (frames) and transmit it over
a high speed serial line, while
minimizing the user's necessary
interface to the high speed cir-
cuitry. In order to accomplish this
task, the HDMP-1022 performs
the following functions:
Parallel Word Input
High Speed Clock Multiplication
Frame Encoding
Parallel to Serial Multiplexing
PLL/Clock Generator
The Phase Lock-loop and Clock
Generator are responsible for
generating all internal clocks
needed by the transmitter to
perform its functions. These
clocks are based on a supplied
frame clock (STRBIN) and control
signals (M20SEL, MDFSEL,
EHCLKSEL, DIV1, DIV0). In
normal operation (MDFSEL=0),
STRBIN is expected to be the
incoming frame clock. The PLL/
Clock Generator locks on to this
incoming rate and multiplies the
clock up to the needed high speed
serial clock. Based on M20SEL,
which determines whether the
incoming data frame is 16 or 20
bits wide, the PLL/Clock Gener-
ator multiplies the frame rate
clock by 20 or 24 respectively
(data bits + 4 control bits). DIV1/
DIV0 are set to inform the
transmitter of the frequency range
of the incoming data frames. The
internal frame rate clock is
accessible through STRBOUT and
the high speed serial clock is
accessible through HCLK.
When MDFSEL is set high, the
transmitter is in Double Frame
Mode. Using this option, the user
may send a 32 or 40 bit wide data
frame in two segments while
supplying the original 32 or 40 bit
frame clock at STRBIN. Doubling
of the frame rate is performed by
Figure 4. HDMP-1022 Transmitter Block Diagram.
ED
CONTROL
LOGIC
+
C-FIELD
ENCODER
FF
CAV*
DAV*
FLAG
D0-D19
RST*
D-FIELD
ENCODER
LATCH
LATCH
SIGN
FRAME
MUX
RFD
FLAGSEL
M20SEL
STRBIN
EHCLKSEL
DIV0
DIV1
MDFSEL
PLL / CLOCK
GENERATOR
ACCUMULATE / INVERT
OUTPUT
SELECT
CAP0
CAP1
0.1 F
STRBOUT
HCLK
LOCKED
DOUT
LOUT
LOOPEN
INV
INTERNAL
CLOCKS
INPUT
LATCH