SCDCT1611 Rev A
GENERAL
The CT1611 provides a complete Bus Controller and Remote
Terminal interface between the MIL-STD-1553B chip set (CT1561,
CT1602, CT1610, etc.) and most microprocessor-based systems
(F9450A, 68000, 8086, VME bus, Multibus, etc.). The unit is
constructed totally with CMOS technology and includes a custom
CMOS chip, two HC CMOS FIFO's and HCT CMOS buffers. Thus
the interface has extremly low power requirements.
The CT1611 interface permits the use of all 15 mode codes and all
types of data transfers as specified in MIL-STD-1553B in both Bus
Controller and Remote Terminal operating modes. A Remote Terminal
is capable of switching to a Bus Controller when requested via the
Dynamic Bus Control mode code.
DATA TRANSFERS
Data transfers in both Bus Controller and Remote Terminal operation
are performed via a DMA burst. This powerful feature insures that the
host microprocessor system will never be held up more than 16.5 usec
when transferring 32 data words into or out of the interface. It also
insures that only good and complete messages will be transferred to
the host's memory. Operation of the DMA is as follows: When data is
received from the 1553 cable via the chip set, it is loaded into an
internal FIFO at the 20 sec/word 1553 rate. Once the complete
message has been received and has passed all validity tests, the
CT1611 issues the signal DMA REQ to the subsystem. (This signal
corresponds to a HOLD request in many systems.) The host
microprocessor then acknowledges and grants this request by issuing
the signal DMA ACK. The CT1611 then becomes the bus master of
the subsystem and transfers all the data on a memory-mapped basis.
When the transfer is complete, the CT1611 removes its DMA REQ
and returns control of the microprocessor bus to the microprocessor.
When data is to be transmitted on the 1553 cable, a similar DMA takes
place. Data is preloaded into the FIFO via a single DMA burst and
then transmitted.
As a failsafe, an internal timeout is provided to insure that the CT1611
can never control the microprocessor bus longer than 80 sec. In
addition, a hard-wired Master Reset input signal is provided that will
place all output signals in a tri-state condition. Therefore, in the
unlikely condition of a failure in the CT1611, the host microprocessor
system can never be brought down or placed in a non-recoverable
state.
A built-in test function has been included to exercise the DMA
operation and verify the message data path. This function is initiated
by an I/O command from the subsystem.
I/O CONTROL
The CT1611 can be addressed, written to, read from, and programmed
much like any peripheral device located on a microprocessor bus. The
address lines and a device select input signal allow the subsystem to
read or write to the CT1611 as if it were memory. In view of the fact
that microprocessors are becoming very fast, two types of handshake
signals were incorporated into the CT1611, either of which may be
used to permit asynchronous read and write operations. Handshaking
directly with the 9450A, 8085, 8086 and the 6802 is the active high
Ready signal. Handshaking directly with the 68000 or VME and
Multibus busses is the active low Acknowledge signal.
INTERFACING
To accomodate both 8 and 16 bit microprocessor data busses, the
CT1611 data path is pin programmable for either operation. When
operating in 8 bit mode, data is DMA'd in 8 bit bytes and therefore
requires twice the time to be transferred.
Bus control signals are pin programmable for either individual read
and write strobes or a common read/write signal and data strobe.
Individual read and write strobes are used with the Intel 8085, 8086
and Multibus. A common read/write signal and data strobe are used
with the 9450A, 6802, 68000 and VME bus. Two separate pins are
provided for input and output data strobes. These signals may be
connected or kept separate to insure that 1553 data can never be
written into a protected area of memory.
RTU OPERATION
The CT1611 is powered-up and reset as a Remote Terminal. In
addition, in Bus Controller mode, it can be changed into a Remote
Terminal via an I/O command.
In Remote Terminal mode, the CT1611 uses dedicated registers for the
received command word, the sync data word, and the vector word. The
command word register contains a second tier so that receive
command words are double buffered. This feature maximizes the
allowable I/O access time.
Four interrupts are provided to alert the subsystem that a valid
message has been received or transmitted or that a mode command has
CT1611 Microprocessor Interface
Standard Products
DMA Controller with Buffer Memory,
September 16, 2003
www.aeroflex.com
MIL-STD-1750A Compatible
FEATURES
Full Bus Control and RTU Operation
Low Software Overhead
Complete BI-Directional Message Buffer
Memory-Mapped DMA Message Transfers
Simple Programmable Polling Operation in Bus Controller Mode
Pin Programmable for both 8 and 16 Bit Microprocessors
Monolithic construction using linear ASICs
Processed and screened to MIL-STD-883 specs
Aeroflex is a Class H & K MIL-PRF-38534 Manufacturer
MIL-PRF-38534 Compliant Devices Available
2
SCDCT1611 Rev A
been serviced. Use of the interrupts is optional. The interrupt signals
are the same for bus control operation although different in meaning.
Interrupts for received or transmitted data messages are generated
after the DMA transfers have been completed.
The Busy, Service Request, and Subsystem Error bits for the status
word are contained in a dedicated register accessible via I/O. The
Busy bit is set high at power-up as well as via a subsystem reset.
BC OPERATION
The CT1611 is programmable into Bus Controller operation via I/O
from the subsystem. Under Bus Controller mode, there are two
command word registers, a received mode data register, two returned
status word registers, an error latch and a transaction word register.
The first command register is used for all 1553 bus transfers. The
second command register is for the second command word used in
RT to RT transfers or for the associated mode data required for
certain mode codes.
The CT1611 provides full validity checking for all 1553 transfers
and alerts the subsystem, via interrupts, as to whether the transfer
was valid or not. The two status word registers are preset high at the
initiation of a transfer and may be read at completion. The second
status word is provided for RT to RT transfers. The error latch may
be used to determine the nature of a failure should a transfer be
unsuccessful.
The transaction word register is used to define the type of transfer to
be performed, to which bus the transfer is to be made, and to define
which bits (when set) in the returned status word constitute an invalid
transfer.
A polling operation has also been included that enables the CT1611
to automatically load the command words and transaction words
from main memory via DMA. This function allows a
preprogrammed polling sequence of the remote terminals to be
implemented with a minimum of subsystem intervention.
3
SCDCT1611 Rev A
Absolute Maximum Ratings
Parameter
Range
Units
Operating Free-air Temperature
-55C to +125
C
Storage Case Temperature
-55C to +155
C
Supply Voltage (V
DD
)
-0.3 to +7
Volts
Input and Output Voltage at any Pad
-0.3 to V
DD
+0.3
Volts
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Supply Voltage V
DD
4.5
5.0
5.5
V
Operating Temperature
-55
-
+125
C
Electrical Characteristics
(V
DD
= +5.0V 10%, T
A
= -55
C to +125C, unless otherwise specified)
Parameter
Conditions
Min
Max
Unit
V
IH
High Level Input Voltage
2.0
-
V
V
IL
Low Level Input Voltage
-
0.8
V
I
IN
Input Current
-10
+10
A
I
IL
Low Level Input Current
Note 4A
-25
-400
A
I
IH
High Level Input Current
Note 4B
-25
-400
A
V
OH
High Level Output Voltage
Note 1
2.4
-
V
V
OL
Low Level Output Voltage
Note 2
-
0.4
V
I
DD1
Quiescent Supply Current
Note 3
5
30
mA
I
DD2
Dynamic Supply Current
Note 5
-
200
mA
Note 1. I
OH
= -2mA for I/O BUS, ADDRESS, R/W & STROBE signal pads
(FP and DIP Pins 12->27 / 28->33 / 5,7)
I
OH
= -1mA for OUTPUT ONLY signal pads
(FP Pins 1->3,6,9,10,39->42,55->58,65,67->69,79,81->83)
(DIP Pins 1->3,6,9,10,39->42,57->60,67,69->71,81,83->85)
Note 2. I
OL
= 4mA for I/O BUS, ADDRESS, R/W & STROBE signal pads
(FP and DIP Pins 12->27 / 28->38 / 5,7)
IOL = 2mA for OUTPUT ONLY signal pads
(FP Pins 1->3,6,9,10,39->42,55->58,65,67->69,79,81->83)
(DIP Pins 1->3,6,9,10,39->42,57->60,67,69->71,81,83->85)
Note 3. Bidirectional I/O at V
DD
(FP Pins 12->27 / 28->38 / 45->52 / 5)
(DIP Pins 12->27 / 28->38 / 47->54 / 5)
I/O Address Lines (FP and DIP Pins 34->38) at V
DD
, remaining OUTPUTS = N/C, remaining INPUTS at V
DD
, MRB at V
IL
< 0.4V.
Note 4. For INPUTS
(FP Pins 59,62,63,64,66,77,86)
(DIP Pins 61,64,65,66,68,79,88)
@V
DD
= 5.5V
A. @V
IL
= 0.4V
B. @V
IH
= 2.4V
Note 5. During typical 32 Word DMA (Output Loading = 0)
4
SCDCT1611 Rev A
DMA
BIDIRECTIONAL
32 WORD
DATA BUFFER
FIFO
8 OR 16 BIT
SUBSYSTEM
DATA BUS
ADDRESS
AND
CONTROL
SIGNALS
INTERRUPTS
0
1
2
3
1
6
BI
T I
N
TE
R
N
A
L
D
A
T
A
BU
S
TO SUBSYSTEM
TO PROTOCOL HYBRID
IH
8 BI
T
I
N
TERNAL HI
GHWAY
(REGISTERS)
00
02
0C
0A
36
38
3C
3A
32
0E
34
BC CW1
TRANSACTION WD
OPERATION WD
RTU RCV CW
ERROR
POLL TRANS OFFSET
LAST POLL TRANS ADD
BC CW2 / AMD / VEC
RTU CW
STAT WD1
STAT WD2 / RMD / SYNC
I/O
DECODER
DMA
CONTROLLER
BIDIRECTIONAL
I/O DATA
BUFFER
INTERRUPT
GENERATOR
BUS
CONTROLLER
SEQUENCER
WATCH DOG
DMA
TIMER
HANDSHAKE
AND
CONTROL
CT1611 FUNCTIONAL BLOCK DIAGRAM
5
SCDCT1611 Rev A
6
5
4
7
8
1
2
3
10
11
21
20
3
7
12
16
22
31
6
5
4
7
8
1
2
3
1
2
30
29
6
.
8F
T1
T2
+
+
0
.
01F
6.8
F
0.01
F
14
25
27
17
20
15
6
35
36
8
5
34
23
32
19
28
24
33
4
9
13
18
DA
T
A
DA
T
A
Bus
"
A
"
St
u
b
Cou
pl
ing
+5V
2K
2K
T1 - T2 a
r
e
T
e
c
h
n
i
tr
ol
X
-
1296
-
1
or
T
-
15
53-
2
**
(
S
ee Note
4)
Dr
i
v
er
/
Rec
ei
v
e
r
P
i
n
o
u
t
s
s
how
n a
r
e
f
o
r
CT148
7
D a
n
d C
T
148
7
DF
Al
l S
e
r
i
e
s
CT148
7
, C
T
158
9, CT3
231
and
CT323
2
a
r
e
ful
l
y
c
o
m
p
at
ab
le
(7
1
)
6
9
(5
6
)
5
4
(5
7
)
5
5
(7
2
)
7
0
(7
3
)
7
1
(7
0
)
6
8
(6
7
)
6
5
(5
8
)
6
6
(1
) 1
(4
5
)
(4
6
)
(9
0
)
8
8
(4
8
)
4
6
(4
9
)
4
7
(5
0
)
4
8
(5
1
)
4
9
(5
2
)
5
0
(4
7
)
4
5
(6
1
)
5
9
(6
6
)
6
4
(
75)
73
(
63)
61
(6
4
)
62
(6
2
)
60
(8
0
)
78
R
T
A
D
0R
T
A
D
1R
T
A
D
2R
T
A
D
3R
T
A
D
4
R
T
A
D
P
A
R
T
e
r
m
in
al
Ad
dr
es
s +
P
a
r
i
t
y
(
O
DD
)
**
*
MIL
-
P
R
F-
15
53B
Ch
ip
Se
t
U
s
e
(
X
X
)
Num
be
r
s
CT16
10, C
T
161
2
, a
n
d C
T
1560
Thr
u
C
T
1563
ar
e fu
ll
y
co
mp
atab
il
e
Te
s
t
P
o
i
n
t
s
(
M
a
y
be
us
ed)
(6
2
)
60
(6
4
)
62
(6
3
)
61
(8
0
)
78
(6
6
)
64
(
8
6)
84
6 (
6
9
)
7 (
7
)
8 (
8
)
9 (
9
)
2 (
2
)
82 (
8
4)
83 (
8
5)
86 (
8
8)
87 (
8
9)
84 (
8
6)
3 (
3
)
4 (
4
)
5 (
5
)
14 (
1
4)
15 (
1
5)
76 (
7
8)
74 (
7
6)
85 (
8
7)
81 (
8
3)
80 (
8
2)
79 (
8
1)
10 (
1
0)
11 (
1
1)
12 (
1
2)
72 (
7
4)
13 (
1
3)
19 (
1
9)
20 (
2
0)
21 (
2
1)
16 (
1
6)
23 (
2
3)
18 (
1
8)
25 (
2
5)
26 (
2
6)
28 (
2
8)
27 (
2
7)
57 (
5
9)
32 (
3
2)
31 (
3
1)
34 (
3
4)
36 (
3
6)
37 (
3
7)
38 (
3
8)
39 (
3
9)
40 (
4
0)
41 (
4
1)
42 (
4
2)
43 (
4
3)
44 (
4
4)
(4
7
)
4
5
(4
8
)
4
6
(4
9
)
4
7
(5
0
)
4
8
(5
1
)
4
9
(5
2
)
5
0
(5
3
)
5
1
(5
4
)
5
2
(5
5
)
5
3
(5
6
)
5
4
(5
8
)
5
6
(5
7
)
5
5
(5
9
)
5
7
(6
7
)
6
5
(6
5
)
6
3
(6
3
)
6
6
(6
9
)
6
7
(7
6
)
7
4
(7
0
)
6
8
(7
8
)
7
6
(7
3
)
7
1
(7
4
)
7
2
(7
5
)
7
3
(7
7
)
7
5
(7
9
)
7
7
(8
3
)
8
1
(8
4
)
8
2
(8
5
)
8
3
(8
7
)
8
5
(8
8
)
8
6
(8
9
)
8
7
(1
)
1
(
81)
7
9
(4
6
)
(4
5
)
(7
1
)
6
9
(8
2
)
8
0
(7
2
)
7
9
(7
9
)
7
7
(6
5
)
6
3
(5
8
)
5
6
(5
5
)
5
3
(5
4
)
5
2
(5
3
)
5
1
(2
4
)
2
4
(1
7
)
1
7
(2
2
)
2
2
(3
0
)
3
0
(2
9
)
2
9
(7
7
)
7
5
(
60)
58
67
(
6
9)
3
3
(
3
3
)
58
(
6
0)
88 (
9
0)
4
4
(
4
4)
SS
ER
R
SYN
C
43
(
4
3)
59
(
6
1)
2 (
2
)
3 (
3
)
4 (
4
)
5 (
5
)
39
(
3
9)
40
(
4
0)
41
(
4
1)
42
(
4
2)
10
(
10)
11
(
11)
5 (
5
)
6 (
6
)
7 (
7
)
8 (
8
)
38
(
38)
37
(
37)
36
(
36)
35
(
35)
34
(
34)
33
(
33)
32
(
32)
31
(
31)
30
(
30)
29
(
29)
28
(
28)
27
(
27)
26
(
26)
25
(
25)
24
(
24)
23
(
23)
22
(
2
2)
21
(
21)
20
(
20)
19
(
19)
18
(
18)
17
(
17)
16
(
16)
5 (
5
)
14
(
14)
13
(
13)
12
(
12)
+5V
RE
SE
T
DB
RE
Q
* T
y
pi
cal
P
i
n o
u
ts
sh
o
w
n f
o
r
Sp
ect
r
um
T
e
c
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og
y
Ser
i
es
7111
T
T
L
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l
e
ad
f
l
at
-
p
a
c
k
.
P
o
ss
ib
le
al
ter
nate
,
Q
-
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T
21
T
T
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ac
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a
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n c
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atab
le
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pec
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um T
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.1F
+5V
GND
+
15V
-
15V
+5
V
+
15V
-
15V
+5
V
+5
V
11
20
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p
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MA
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R
PA
R
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LT
F
A
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L
HS
F
A
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E
RRO
R
T
e
s
t
P
o
i
n
ts
(
M
a
y
b
e
us
ed
)
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ubs
ys
tem
Contr
o
l
,
Han
d
sh
ak
e an
d
I
n
ter
r
upt L
i
ne
s
Sub
s
y
s
te
m
I/O
Add
r
e
s
s
(
1
0 L
i
ne
s
)
Sub
s
y
s
te
m
I/O
Add
r
e
s
s
(
1
6 L
i
ne
s
)
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ar
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r
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e
s
e
t fr
o
m
Sy
s
t
e
m
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w
e
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on
r
e
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e
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C
n
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1 &
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1553
-
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e i
denti
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l
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t
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-
155
3-
2
5
.
Inte
r
r
up
t Func
tio
n
s
:
SIG
N
A
L
BC M
ode
RT
U
M
o
d
e
IN
T
R
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IN
T
R
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IN
T
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T
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er
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ta
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(
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)
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Res
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C
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6. A
C
K
,
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hand
sha
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s I/O
Da
ta tr
ans
f
e
r
s
. E
i
the
r
si
gnal
m
a
y
be
us
ed de
pend
ing
on s
y
s
t
em
r
e
qui
r
e
ments.
7. DM
A D
A
T
A
A
C
K
ma
y
b
e
us
ed to
e
x
ten
d
the
data
t
r
a
n
s
f
er
ti
me d
u
r
i
ng
DMA
.
8. P
i
n
69 d
e
fin
e
s
P i
n
ter
f
ac
e
,
i.e
R/W
, &
STRBD
or
AD
S
T
B
&
WR
TSTB
.
(
P
in
s 7
& 8
m
u
s
t
be
tied
D
U
AL
Red
undan
t
BC/
R
TU
15
53B T
o
P I
n
te
rf
ace
RT
A
D
P
A
R
RT
A
D
4
RT
A
D
3
RT
A
D
2
RT
A
D
1
RT
A
D
0
NC
NC
NC
NC
Rx
D
A
T
A
1
E
RRO
R
Tx
IN
H 1
Rx
D
A
T
A
1
RT
A
D
E
R
TX
T
O
MA
N
E
R
PA
R
E
R
LT
F
A
I
L
MS
F
A
IL
I
H715
I
H614
I
H513
I
H412
I
H311
I
H210
IH
19
IH
08
IH
E
N
IHDIR
RE
Q
B
US
B
RE
Q
B
US
A
RT
0
BC
OP
S
T
B
BC
OP
B
BC
OP
A
DT
A
C
K
DT
R
Q
IU
S
T
B
SY
N
C
NB
GT
VE
CTE
N
/D
W
E
N
EO
T
SE
R
V
RF
Q
IN
CM
D
ST
A
T
EN
/
S
T
A
TS
TB
H/
L
GB
R
LS
TCMD
/C
W
E
N
BI
T
E
N
/R
M
D
S
T
B
BUS
Y
SS
ER
A
DB
A
C
C
CW
C4
CW
C3
CW
C2
CW
C1
CW
C0
WC
4
WC
3
WC
2
WC
1
WC
0
SA
4
SA
3
RT
/
B
C
SA
2
SA
1
SA
0
Tx D
A
T
A
Tx D
A
T
A
Rx
D
A
T
A
0
Tx
INH
0
INCL
K (
2
MH
z C
l
o
c
k
)
ND
RQ
Tx
/
R
x
CM
SY
NC
+5V
IN
C
T
160
2
MIL-P
RF-155
3B
Rx
D
A
T
A
0
BUFI
N
H
BC
S
T
EN
0
BC
S
T
EN
1
VA
L
D
DW
S
Y
N
C
DB
RE
Q
RES
E
T
PA
S
M
O
N
GND
/
CASE
6 M
H
z
C
h
ipset
***
IH
715
IH
614
IH
513
IH
412
IH
311
IH
210
IH
19
IH
08
IH
E
N
IH
DIR
RE
Q
B
US
B
RE
Q
B
US
A
RT
0
BC
OP
STB
BC
OP B
BC
OP A
DT
A
C
K
DT
RQ
IU
S
T
B
SY
NC
NB
G
T
VE
CTE
N
/D
W
E
N
EO
T
SE
R
V
R
F
Q
IN
CM
D
ST
A
T
EN
/
S
T
A
TSTB
H/L
GBR
LS
T
C
MD
/C
W
E
N
BI
TEN
/R
M
D
S
T
B
BU
S
Y
SS
ER
A
DB
A
C
C
CT
16
11
DMA Contr
o
lle
r
P
r
o
cess
o
r
In
t
e
rf
ace
with FIFO
I
n
ter
r
upt
Ou
t
p
u
t
s
R
T
AD
ER
TX
T
O
MA
N
E
R
PA
R
E
R
HS
F
A
I
L
LT
F
A
I
L
(L
SB
)
D
0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1
0
D1
1
D1
2
D1
3
D1
4
(M
S
B
)
D
1
5
(L
SB
) A0
A1
A2
A3
A4
A5
A6
A7
A8
(
MSB
) A9
NC
(A10,
8 Bit
M
ode only
)
(ST
R
BD
/W
R
S
T
B
)
S
T
RB
DI
STRB
DO
OU
T
(ST
R
BD
/W
R
S
T
B
)
IN
RD
Y
D
R/W
(R
/
W
, RD
S
T
B
)
DM
A
R
EQ
DM
A
A
C
K
IN
T
2
IN
T
0
IN
T
1
IN
T
3
AC
K
DE
VI
C
E
S
E
L
TR
AN
S
M
I
T
/
R
EC
EI
VE
MA
ST
E
R
RE
S
E
T
DMA
D
A
T
A
A
C
K
PO
LL
/
D
A
T
A
COM
M
ON
/
C
AS
E
+5V
IN
6 M
H
z
RT
/
B
C
16
/
B
MO
D
E
0
/M
O
D
E
1
NC
NC
NC
NC
NC
NC
Rx
D
A
T
A
IN
2
Tx
D
A
T
A
OUT 2
Tx
D
A
T
A
OUT 2
Rx
D
A
T
A
IN
2
Rx
D
A
T
A
IN
1
Tx
D
A
T
A
OUT 1
Tx
D
A
T
A
OUT 1
Rx
D
A
T
A
IN
1
GN
D
G
N
D
GN
D
G
N
D
GN
D
GN
D
Rx
D
A
T
A
OUT 2
Rx
D
A
T
A
IN 2
Tx INHI
B
I
T 2
Tx
D
A
T
A
IN 2
T
x
D
A
T
A
IN 2
ST
R
O
B
E
2
ST
R
O
B
E
1
T
x
D
A
T
A
IN 1
Tx
D
A
T
A
IN 1
Rx
D
A
T
A
OUT 1
Rx
D
A
T
A
OUT 1
Tx
INHI
BIT
1
C
T
-
1
487
D a
nd DF
D
u
al D
r
ive
r
/
R
ecei
ver
**
(1)
(
2)
(1)
(
2)
(2)
(1)
+
1
5V
+
1
5V
+5V
+
5V
-15V
-15V
DA
T
A
DA
T
A
Bus
"
B
"
St
u
b
Cou
pl
ing
NO
TE
S
:
1
.
XX
Pi
n numbe
r
s
ar
e f
o
r
fl
at pa
c
k
s
2.
(
X
X)
Pi
n n
u
mb
e
r
s
ar
e f
o
r
pl
u
g
i
n
p
a
c
k
a
g
e
3. P
i
n
n
u
m
ber
s
f
o
r
CT
14
87D (
P
l
ug i
n
)
and
CT
1487
DF
(
f
l
a
t p
a
c
k
)
ar
e th
e s
a
me
.
4
.
Pi
n n
u
mb
e
r
s
f
o
r T1
& T2
in
D
I
P
& F
l
at P
a
c
k
pac
k
age
ar
e the
sa
me
.
X
-
1269-
1 (
D
IP
)
X-
126
9-
1
F
P (
F
lat
P
a
c
k
)
T
-
155
3-
2 (
D
IP)
T
-
155
3-
2F
P (
F
lat
P
a
c
k
)
CT
1608
F
P
&
CT
1
611F
P
.
CT
1608
& CT
16
11.
ha
s g
uar
ant
eed -
5
5
C Inp
u
t Imp
edan
ce
23K
pe
r
M
I
L-
ST
D-
155
3B
.
t
ogeth
e
r
)
V
CC
6M
H
z
O
sci
llat
o
r
GND/
C
a
s
e
Ou
t
*
CT1
611
T
y
pical Application
14
7
T
e
s
t
P
o
i
n
ts
(M
a
y
b
e
Us
ed)
6
SCDCT1611 Rev A
CT
1611
User's Guide
7
SCDCT1611 Rev A
10010
11101
0
00011
18
0
29
3
Receive Command Register
Word
Count
Sub-
Address
RT
Address
CW
DW1
DW2
DW3
SW
Subsystem
Address
Memory
Data
11101
11101
11101
XXX
XXX
XXX
00010
00001
00000
DW1
DW2
DW3
Subsystem
Address
29
Continuous
word count
address selector
MSB's
determined by
subsystem
Example of DMA Data Transfer
Transfer = 3-Word Receive Message in RTU Mode
T/R
8
SCDCT1611 Rev A
TRISTATE
TRISTATE
TRISTATE
TRISTATE
Tristate with Pullup
200ns to 400ns
60ns MAX (Note 1)
100ns MAX
DATA Latched
180ns to 375ns
65ns MAX
Tristate with Pullup
R / W
ADDRESS
DEVICE SELECT
STRBD
RDYD
DATA
ACK
(From UP System)
(From UP System)
(From UP System)
(From UP System)
(From DMA Controller)
(From DMA Controller)
(From up System)
ADDRESS VALID
VALID
I / O WRITE OPERATION
Notes:
1. Measured from STRBD or DEVICE SELECT whichever is valid LAST.
RDYD requires the coincidence of STRBD and DEVICE SELECT.
TRISTATE
TRISTATE
TRISTATE
Tristate with Pullup
200ns to 400ns
60ns MAX (Note 1)
100ns MAX
180ns to 375ns
65ns MAX
Tristate with Pullup
R / W
ADDRESS
DEVICE SELECT
STRBD
RDYD
DATA
ACK
(From UP System)
(From UP System)
(From UP System)
(From DMA Controller)
(From DMA Controller)
(From DMA Controller)
(From up System)
I / O READ OPERATION
Notes:
1. Requires BOTH STRBD or DEVICE SELECT to be LOW.
2. DATA will be valid 100ns before RDYD goes HIGH, and ACK goes LOW.
ADDRESS VALID
VALID
TRISTATE
40ns MIN
100ns MIN (Note 2)
65ns MAX
9
SCDCT1611 Rev A
TRISTATE
LAST
FIRST
TRISTATE
666ns
500ns
50ns MIN
Extended 1 Cycle
50ns MIN
DMA ACK
(From UP System)
65ns MAX or Cycle Extended
250ns MIN
250ns MIN
330ns MAX
0ns MIN /27s MAX
DMA REQ
(From DMA Controller)
DMA DATA ACK
(From UP System)
DMA STRBD
(From DMA Controller)
Tristate pulled HIGH
Tristate pulled HIGH
500ns
500ns TYP
100ns MAX
VALID MSG RCV'D
(Interrupt from DMA Controller)
ADDRESS / DATA
(From DMA Controller)
R / W
(From DMA Controller)
Notes:
1. If a DMA DATA ACK is not implemented in system, DMA DATA ACK should be
2. Preferred method for resetting DMA DATA ACK HIGH is with trailing edge of DMA STRBD.
DMA WRITE OPERATION
TRISTATE
ADDRESS
DATA
DMA REQ
(From DMA Controller)
(From UP System)
(From DMA Controller)
Notes:
1. R / W from DMA Controller = Logic "1".
2. DATA will be valid within 220ns of STRBD or VALID with DMA DATA ACK.
LAST
FIRST
TRISTATE
TRISTATE
VALID
TRISTATE
666ns
500ns
50ns MIN
Extended 1 Cycle
120ns MAX or Cycle Extended
50ns MIN
333ns MIN
250ns MIN
220ns MAX
330ns MIN
Note 2
0ns MIN / 18s MAX
100ns MIN
DMA ACK
(From UP System)
DMA DATA ACK
(From UP System)
DMA STRBD
(From DMA Controller)
DMA READ OPERATION
either connected to DMA STRBD (preferred) or tied LOW.
10
SCDCT1611 Rev A
Summary of I/O Commands for CT1611 1553B Interface
(All Codes HEX)
Bus Controller I/O
Address
Code
(8 Bit Mode)
Description
(Read or Write)
Command Word # 1
XX00 (Low)
XX01 (High)
All Transfers
(Read or Write)
Command Word # 2
XX02
1. Second command word for RT to RT Transfers
2. Also associated mode data for mode change such as sync w/data
3. Also used for RTU vector word
(Read or Write)
Transaction Word
XX0C
Defines type of transfer and BUS selection
(Write Only)
Trigger
XX2A
Triggers Bus Transaction
Note: Command word(s) and transaction code must be loaded
(Read Only)
Status Word 1
XX3C
Return status word for all transactions (first for RT to RT).
Note: This register is preset to FFFF at beginning of transaction and
at reset.
BC (Read Only)
Status Word 2
Rtn'd Mode Data
XX3A
Second returned status word for RT to RT xfers, also preset FFFF.
Also returned mode data, such as vector word and last command.
RTU (Read Only)
Sync w/Data
Sync Word
(Read Only)
Command Word
XX36
Received command word for all transactions. i.e. transmit, receive*
and mode.
* use XX38
(Read Only)
Receive Command Word
XX38
Double Buffered version of above for valid receive commands
(provides more I/O time).
(Read or Write)
Vector Word
XX02
Mode Data
-to be transmitted
- same reg as CW # 2
Examples
Function
Data
Normal xfer
Normal xfer
Bus 0
Bus 1
0000
0008
RT to RT
Bus 0
Bus 1
0001
0009
Mode (No Data)
Mode (No Data)
Bus 0
Bus 1
0003
000B
Mode (Rtn'd Data), i.e. vector word last
cmd, etc.
Bus 0
Bus 1
0005
000D
Mode (ass'td Data), i.e. sync w/data
Bus 0
Bus 1
0007
000F
11
SCDCT1611 Rev A
RTU Mode
1.
Conditions for Busy
When the CT1611 is declared busy, the DMA data transfer operation is inhibited. Mode data is stored in internal registers, and is
therefore unaffected by busy. The bust bit is located in the Operation Register.
1.1
Busy Set by I/O and POR / RESET
1.2
DMA not complete
(This in general should never occur).
1.3
FIFO Test
1.4
Receive Commands
If a Terminal is declared busy during the reception of a valid message, that message will be received and a DMA
request will be generated.
Data will be held indefinately until the DMA request is acknowledged.
Once the DMA is completed, a valid message received interrupt will be generated.
1.5
Transmit Commands
If the subsystem is going to enter a non-interruptable mode and therefore declares itself busy and the condition exists
that a transmit command may be received "simultaneously", the subsystem should wait 6sec before beginning. (If a
DMA request is not made during this time, none will be made until the terminal is declared not busy).
This insures:
a.
HSFAIL will not occur because of the busy condition missing the command word.
b.
DMA issued, that can't be acknowledged at a "non-interruptable time" by the microprocessor subsystem.
(Read Only)
Sync Word
XX3A
1. Mode Data
-to be received
2. Same as returned mode in BC mode
(Write Only)
Reset I
XX2E
Resets CT1611 interface only
(Write Only)
Reset II
XX2C
Resets CT1611 and CT1610 front end, will reset bits in returning
status word such as "TF" flag. Same as hard wired master reset used
on power up.
(Read or Write)
Operational word
XX0A
Defines BC mode and RTU mode.
Data
FFF0 = RTU
FFF1 = BC
Note: Powers up and is reset to busy RTU.
Summary of I/O Commands for CT1611 1553B Interface
(All Codes HEX)
Bus Controller I/O
Address
Code
(8 Bit Mode)
Description
12
SCDCT1611 Rev A
Interface Mode
MODE 1 / MODE 0
"0" is Motorola/Fairchild 9450 compatibility
"1" is Intel compatibility
Operational Commands
other than register reads and writes
M1 / M0
Write Operations
Read Operations
0
RDSTB / R/W
R/W
WTSTB / STRBD
STRBD
R / W = 0
STRBD =
- Same-
R / W = 1
STRBD =
1
RDSTB / R / W
RDSTB
WTSTB / STRBD
WTSTB
RDSTB = 0
WTSTB =
- Same-
RDSTB =
WTSTB = 1
Operation
Op Code (DS = 0)
Test Triggers - must be in test mode, otherwise no operation results
FIFO Reset
Test trigger (load)
Test trigger (unload)
Operational Triggers
X10100X
XX28
H
Must be
in poll
mode
START POLL (from offset)
START POLL (from 0)
(resets offset reg.) Reg. Address 000E
H
CONTINUE POLL (from next address)
CONTINUOUS MODE- starts new poll
from beginning after "poll op cmplt" INTERRUPT
Non-CONTINUOUS - "poll op cmplt" INTERRUPT
- then no action
Note: Trigger (does not load new cmd WD (1) or transaction) generally
used for non chained poll, single transaction in polling mode. This
operation will repeat last, then continue.
X10000X
X10001X
X10010X
XX20
H
XX22
H
XX24
H
Resets
Reset I resets interface only
Reset II same as master reset (hardware), also resets chip set
X10111X
X10110X
2E
H
2C
H
Note: All Operational Codes are Write Operations.
13
SCDCT1611 Rev A
BC Criteria for Valid Transactions
Valid Transactions result in generation of GOOD XFER (INT 0) Interrupt.
Invalid Transfer result in generation of INVALID TRANSFER (INT 1) Interrupt.
See Transaction Word for additional Status Word Criterion (i.e. bit masks)
General Validity Criteria - Applies to all transfers
A. Bus must be quiet, i.e. no additional data words, status words or command words after correct RT response
before transaction is declared valid.
B. If data is returned, word count, must be correct. Data must also be contiguous, i.e. no gaps.
C. RTU Address(s) must be correct in returned status word(s).
D. RTU must respond within 14sec (except for non RT to RT Broadcast).
E.
No bits set in returned status word(s), except where masked in transaction word.
Interrupts In BC Mode
Transaction Type
Specific Validity Criteria
1. Normal Data Transfer
A. RT to BC
B. BC to RT
C. Broadcast
(Tx/Rx = 1)
(Tx/Rx = 0)
(Tx/Rx = 0)
Status, then Valid Message
Status
No Status
2. RT to RT Transfer
A. Normal
B. Broadcast
(Tx/Rx = 1)
(Tx/Rx = 1)
Status, Valid Message,then Status
Status, then Valid Message only
3. Mode (no data)
A. Normal
B. Broadcast
Status
No Status
4. Mode (associated data)
A. Normal
B. Broadcast
Status
No Status
5. Mode (returned data)
Status, then returned data
BC Interrupt Name
Signal Name
Conditions and Actions
Good Transfer
INT 0
1. Indicates fully valid transaction.
2. Initiates next poll operation, when in polling mode.
Invalid Transfer
INT 1
1. Non masked bits set (includes reserved bits).
2. No status (2 for non BCST RT to RT) word returned.
3. Status word has incorrect address.
4. Fail safe time out (1 millisec)for bus (RTU) to go quiet i.e.
RTU loudmouthing.
5. Incorrect number of data words.
6. Busy (even if busy masked) when RTU should receive or
transmit data.
Note: busy mask only masks busy for mode cmds.
Poll Operation Complete
INT 2
1. Indicates end of poll,when end of poll is a valid transaction.
2. Delayed from good transfer interrupt.
3. Initiates poll sequence again (from offset) if in continuous
mode.
4. If the I/O command "continue at next transaction" is issued at
the last transaction command, this interrupt will be issued.
14
SCDCT1611 Rev A
Interrupts in RTU Mode
Bus Controller Poll Operation
RTU Interrupt Name
Signal Name
Conditions and Actions
Valid Message Received
INT 0
1. Indicates the reception of a complete and valid block of data.
2. Interrupt issued after complete block of data has been DMA'd to
subsystem memory.
3. Command word for receive data block is located in double
buffered receive command register.
SYNC With Data
INT 1
1. Issued after reception of valid SYNCHRONIZE with data mode
command. (Interrupt is not generated if word count is high).
2. Command word located in command register.
3. SYNC data word located in SW2/RMD register.
Mode W/O Data
INT 2
1. Indicates reception of mode commands without data that may
require subsystem action. These are:
SYNCHRONIZE (W/O DATA)
RESET
DYNAMIC BUS CONTROL ACCEPTANCE
2. Command word located in command register.
Data Transmitted
INT 3
1. Indicates reception of valid transmit command or vector mode
command.
2. If issued for transmit command,then issued after DMA.
3. If issued for vector, data transmitted from CW2/AMD/VEC
register.
4. Command word located in command register.
Internal Triggers
Op Code
Trig A
continues operation
conditions -
transaction
-poll op enabled
-BC mode
XX24
Trig B
begin again (from offset)
conditions
- transaction = last (TB6 = 0)
- poll op enable
- BC mode
- valid trans interrupt
XX20
15
SCDCT1611 Rev A
Summary of Registers
Register Name
General Function
Op Code
BC Command WD 1 Register
1. Contains the command word for all bus transactions (first for RT to RT transfers).
(BC only)
2. Automatically loaded in polling operation.
XX00
CW2 / AMD / VEC Register
1. Used in both RT and BC.
2. Contains second command word for RT to RT transfers. (BC only)
3. Contains associated mode data for mode command requiring transmitted data. (BC
only)
4. Optionally automatically loaded in polling operation. (BC only)
5. Contains vector word. (RTU only)
XX02
Transaction Word Register
1. Contains additional information required to fully define a bus transaction, i.e. bus
selection, transfer type (normal/mode). (BC only)
2. Automatically loaded in polling operation.
XX0C
Transaction Address Register
1. Contains starting address for BC polling operation.
XX0E
Last Transaction Register
1. Contains address of last transaction.
2. Used to determine where in command stack, a failed transaction command is
located.
XX34
Operation Register
1. Sets operational mode i.e. Bus Controller Remote Terminal
2. Control of status word bits in RTU mode:
a. BUSY
b. SSERR
c. SERVRQST
XX0A
Error Latch
1. Contains information on transactions occurring on 1553B bus.
2. Primarily used in bus controller mode. Useful in RTU mode especially during
system debugging.
XX32
RTU Command Word Register
1. Contains all commands received by RTU. (RTU only). Includes normal data and
mode commands.
XX36
RTU Receive Command Word
Register
1. Contains only valid receive commands. (RTU only)
2. Loaded after data block validated.
3. Doubled buffered version of RTU command word register.
XX38
Stat Word 1 Register
1. Contains returned status word. (BC only).
2. Contains first returned status word for RT to RT transfers. (BC only)
XX3C
Stat WD2 / RMD Register
1. Contains second returned status word for RT to RT transfers. (BC only).
2. Contains returned rode data for mode commands. (BC only). Sync word as RTV.
XX3A
16
SCDCT1611 Rev A
1. Power up and reset to busy RTU.
2. Used to define operating mode of 1553 interface, used for both BC and RTU modes
543210
3. Select Code = 00101X 001010 XX0AH DS = 0
Operation Register
MSB
LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reg. Bit
Name
Definition
0
RT/BC
Terminal Mode
0 = RTU Mode
1 = BC Mode
1
POE
Poll Operation Enable
Enables Polling Operation in BC Mode
0 = Not Enabled
1 = Enabled
2
CONT POLL
Continuous Poll Operation Enable causes polling
operation to continuously loop when enabled and active.
0 = Not Enabled
If this bit is reset during an active polling loop, poll will end at
completion of polling frame.
1 = Enabled
3
PFO
Poll Fault Overide
When not enabled, Poll Operation will halt immediately after a transaction
failure. (Invalid Transfer Interrupt Generated).
Note: Poll can be restarted, with last (failed transaction) or next transaction.
When Enabled, poll will continue even if transaction failed.
0 = Not Enabled
1 = Enabled
4,5
REPEAT
If an Error condition is detected in BC mode, the interface can RETRY the
command sequence based on the following table:
The Interface will continue on to the next Transaction if the prescribed number
of REPEAT attempts has transpired and the Error condition is still present.
Bit 5
Bit 4
Repeat Count
0
0
None
0
1
1
1
0
2
1
1
3
17
SCDCT1611 Rev A
6,7
TEST
FIFO Loop Tests
A. 1553 Side Loop
NO DMA occurs
B. SUBYSTEM (Microprocessor) Side Loop
1553 Side Set BUSY
FIFO Exercised via
I/O Test Trigger Load Command
and
I/O Test Trigger Unload Command
8
NO OP
NO OPERATION (Wait) when in poll mode (BC).
9
PACT
POLL ACTIVE
PACT = 1 indicates that a POLLING operation has been triggered.
10
DBCACC
RTU Dynamic Bus Controll Acceptance when set in RTU Mode, Rtu will
accept bus control request as per MIL-PRF-1553B
0 = Not Set
1 = Set
11
SSERR
Sets subsystem error flag in returned status word (RTU Mode Only).
12
BUSY
Sets busy bit in returned status word, inhibits DMA (RTU Mode only).
13
TRANSACT
TRANSFER ACTIVITY
TRANSACT = 1 indicates a Transaction has been initiated and is in progress.
14-15
SERVRQ
Sets Service Request in returned status word (RTU Mode only).
Reg. Bit
Name
Definition
Bit 7
Bit 6
Test
0
0
RESET
1
1
Test A
1
0
Test B
0
1
Not Valid
TEST ENABLE
TEST A/B
Bit 15
Bit 14
Flag
0
0
NOT Set
0
1
SET until reset
1
0
Set until VECTOR word is transmitted
1
1
Set until reset *
* Bit 15 is ALWAYS RESET after VECTOR Word is transmitted.
Operation Register con't
18
SCDCT1611 Rev A
Error Register
MSB
LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
The error Register is reset by: - I/O reg reset command
- I/O reset command
- Power on reset (master reset)
- Initiation of transfer in BC mode
Bit
Name
Indication (When Set)
0*
RTADER
- RTU address Error (Parity)
1*
PARER
- Parity error in command or data word
2*
ERROR
- Any waveform encoding error in received data
- Bad Manchester
- Bad Parity
- Bad Data Sync
- Non Contiguity of data
3*
LTFAIL
- Encoding error in terminals transmission
- Includes RT address parity
4
HSFAIL
- Subsystem has not acknowledged DMA request in sufficient time.
5
TXTO
- Transmitter timeout error indicates 1553 transmitter has transmitted in excess
of 680sec and terminal fail safe timeout has turned off transmitter. NOTE:
1553B Max. is 800s. If terminal timeout hardware (RT) fails self test mode
command (Indicate self test), this bit will also be set.
6
DMA TO
- DMA Time Out
Indicates failure in data transfer between CT1611 and subsystem. If DMA
takes longer than 80sec this flag will be set and DMA will be initiated.
Bit
Name
Definition
7
DBCACC
Dynamic Bus Control Acceptance
Active only in RTU mode.
Indicates RTU has accepted bus controller request.
RTU must switch to BC mode.
8
TRANS TO
Transaction Time Out
Active BC mode only
Indicates BC transfer has failed due to loopmouthing RTU or non functioning
transceive in BC.
Occurs approximately 780sec after transfer is triggered.
Reg. Bits
Indication
3
2
1
0
0
1
0
0
Waveform encoding error (Manchester)
0
1
1
0
Data parity error
1
X
X
1
RTU address error
* Additional information
for interpretation of
Register Bits 0-3.
19
SCDCT1611 Rev A
9
GBR
Good Block Received
Active BC mode only
Indicates valid message has been received by bus
controller, set even if transaction is otherwise
not valid.
10
RMD
Received Mode Data
Active only in BC mode
Indicates valid mode data has been returned from RT.
This bit is set even if transaction is otherwise
not valid.
11
BIT SET
Bit(s) set in returned status word(s). Active in BCC
mode only.
Indicates non masked bits in status word(s) are set.
Masked bits are masked in Transaction Word
Register.
Bits include:
Message error bit
Instrumentation bit
Service Request
Reserved Bit(s) (3 bits)
Broadcast Cmd Rcvd bit
Busy bit
Subsystem Flag
Dynamic Bus Control Acceptance bit
Terminal Flag
12
AD ERR
Address in status word(s) error active only in BC mode.
Indicates RTU address in returned status word(s) is incorrect.
13. 14
SW CNT
Returned status word count.
Active only in BC mode.
Two bit non rollover counter for returned status words..
15
BUS ACT ERR
Bus Activity Error
Active in BC mode only.
This bit is set if the bus is active when should be quiet following:
A. Returned mode data (indicates word count high)
B. After status in normal receive, mode without data, and non broadcast RT
to RT.
Bit
Name
Indication (When Set)
Bit 14
Bit 13
Count
0
0
None returned
0
1
One returned
1
0
Two returned
1
1
Three, or greater returned
Error Register con't
20
SCDCT1611 Rev A
Used only in BC mode
Contains information not explicitly contained in command word.
Defines:
1. Type of Transfer
2. Selection of bus
- selects 1 of 4
Note: Most
systems
are only dual
redundant
3. Continue, for continuous poll operation
4. Conditions for defining an invalid transfer via Bit masks for returned status words.
5. Continue/last control bit for framing poll operations.
This register is loaded via I/O Command. It is also loaded during a Polling Operation, via DMA from the polling
command stack.
Transaction Word Register
MSB
LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reg. Bit
Name
Definition
0 - 2
TRANS TYPE
Specifies Transaction Type
3 - 4
BUS
Selection of Bus
5
DMA3RD
Polling Sequence Option (Polling Mode only)
For use with RT to RT transfers and code with associated data transfers.
When set, during polling sequence, the second command word (for RT to RT
transfers) or the data word (for mode with associated data transfers) is loaded
from the command stack.
Otherwise the last entry in the second command/and register will be used in
transfer.
0 = Not Set
1 = Set
Bit 2
Bit 1
Bit 0
Transaction
0
0
0
NORMAL Receive or Transmit
0
0
1
RT to RT
0
1
0
No Operation
0
1
1
Mode WITHOUT data
1
0
0
No Operation
1
0
1
Mode with RETURNED data
1
1
0
No Operation
1
1
1
Mode with associated data
Bit 4
Bit 3
Bus
0
0
"0" or "A"
0
1
"1" or "B"
1
0
"2" or "C"
1
1
"3" or "D"
21
SCDCT1611 Rev A
6
POLL CONT
Poll Operation Continue (Polling Mode only)
When set polling operation will continue with next
command in command stack.
When Not Set, polling operation will terminate after transaction is complete.
Last transfer in polling sequence must have this bit cleared.
0 = Not Set
1 = Set
7 - 15
MASK BITS
Returned Status Word Bit Masks
1 = Masked
0 = Not Masked
When a non masked bit in the returned status word(s) is set the transaction is
declared not valid
.
Reg. Bit
Name
Definition
Bit Status
Bit
7
Terminal Flag
8
Dynamic Bus Control Acceptance
9
Subsystem Flag
10
Busy Bit *
11
Broadcast Command Received
12
Reserved Bits (any or all of 3)
13
Service Request Bit
14
Instrumentation Bit
15
Message Error Bit
* Note: Setting the busy bit mask will not mask a busy
response (i.e. declare it valid). When data is not
returned, in response to a transmit command.
Transaction Word Register con't
22
SCDCT1611 Rev A
CT1611 Pinouts vs Function
Pin #
Signal
Pin #
Signal
FP
DIP
FP
DIP
1
1
SSERR 88
90
+5V
2
2
TRANSMIT/RECEIVE 87
89
BUSY
3
3
POLL/DATA 86
88
BITEN /RMDSTB
4
4
DS 85
87
LSTCMD /CWEN
5
5
R/W /RDSTB 84
86
HSFAIL
6
6
RDYD
83
85
GBR
7
7
STRBD /WRSTB (OUT)
82
84
H/L
8
8
STRBD /WRSTB (IN)
81
83
STATEN /STATSTB
9
9
ACK 80
82
RT/BC
10
10
DMA REQ 79
81
DBCACC
11
11
DMA ACK 78
80
TXTO
12
12
DB 0
77
79
SERVREQ
13
13
DB 1
76
78
INCMD
14
14
DB 2
75
77
EOT
15
15
DB 3
74
76
DTRQ
16
16
DB 4
73
75
VECTEN /DWEN
17
17
DB 5
72
74
NBGT
18
18
DB 6
71
73
SYNC
19
19
DB 7
70
72
16/8
20
20
DB 8
69
71
MODE 1/MODE 0
21
21
DB 9
68
70
IUSTB
22
22
DB 10
67
69
DTACK
23
23
DB 11
66
68
BCOP A
24
24
DB 12
65
67
BCOPSTB
25
25
DB 13
64
66
RTADER
26
26
DB 14
63
65
BCOP B
27
27
DB 15
62
64
PARER
28
28
AD 0
61
63
MANER
29
29
AD 1
60
62
LTFAIL
30
30
AD 2
59
61
DMA DATA ACK
31
31
AD 3
58
60
CLOCK IN (6MHZ)
32
32
AD 4
57
59
RTO
33
33
AD 5
56
58
REQBUS B
34
34
AD 6
55
57
REQBUS A
35
35
AD 7
54
56
IHDIR
36
36
AD 8
53
55
IHEN
37
37
AD 9
52
54
IH08
38
38
AD 10
51
53
IH19
39
39
INT 3 50
52
IH210
40
40
INT 1 49
51
IH311
41
41
INT 0 48
50
IH412
42
42
INT 2 47
49
IH513
43
43
MASTER RESET 46
48
IH614
44
44
COMMON/CASE
45
47
IH715
-
45
N/C
-
46
N/C
23
SCDCT1611 Rev A
.080 REF
.225
MAX
.010
.002
.015
2.150
Pin 45
.115
Pin 44
2.400
MAX
Date
Code
Lead 1 & ESD
Designator
1.600
MAX
Designator
1.600
MAX
.300
Min
.050 Lead Centers
44 Leads/Side
TYP
Pin 88
Flat Package Outline
Plug In Package Outline
Lead 1 & ESD
Designator
.100
1.100
TYP
2.200
2.100
Pin 43
Pin 45
Pin 44
Pin 2
Pin 3
.135
.050
TYP
1.300
.090
.135
Pin 1
Pin 48
Pin 46
Pin 47
Pin 88
Pin 90
Pin 89
.018 DIA
TYP
2.400
MAX
1.600
MAX
.200
MIN
.225
MAX
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attributes represented by these three icons:
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Aeroflex Microelectronic Solutions reserves the right to
change at any time without notice the specifications, design,
function, or form of its products described herein. All
parameters must be validated for each customer's application
by engineering. No liability is assumed as a result of use of
this product. No patent licenses are implied.
24
SCDCT1611 Rev A
Ordering Information
Model No.
Case
CT1611
Plug In
CT1611-FP
Flat Pack
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ZIP