ChipFind - документация

Электронный компонент: AD5535

Скачать:  PDF   ZIP
www.docs.chipfind.ru
background image
32-Channel, 14-Bit DAC with Full-Scale Output
Voltage Programmable from 50 V to 200 V
Preliminary Technical Data
AD5535
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
High integration: 32-channel, 14-bit DAC with integrated,
high voltage output amplifier
Guaranteed monotonic
Housed in 15 15 mm CSP-BGA package
Full-scale output voltage programmable from 50 V to 200 V
via reference input
700 A drive capability
Integrated silicon diode for temperature monitoring
DSP-/microcontroller-compatible serial interface
Channel update rate: 1.2 MHz
Asynchronous RESET facility
Temperature range: 10C to +85C
APPLICATIONS
Optical micro-electromechanical systems (MEMS)
Optical cross-point switches
Micropositioning applications using Piezo Flextures
Level setting in automotive test and measurement
GENERAL DESCRIPTION
The AD5535 is a 32-channel, 14-bit DAC with an on-chip high
voltage output amplifier. This device is targeted for optical
micro-electromechanical systems. The output voltage range is
programmable via the REFIN pin. Output range is 0 V to 50 V
with REFIN = 1 V and is 0 V to 200 V with REFIN = 4 V. Each
amplifier can source 700 A, which is ideal for the deflection
and control of optical MEMS mirrors.
The selected DAC register is written to via the 3-wire interface.
The serial interface operates at clock rates of up to 30 MHz and
is compatible with DSP and microcontroller interface standards.
The device is operated with AV
CC
= 4.75 to 5.25 V, DV
CC
= 2.7 V
to 5.25 V, V
= -4.75 V to -5.25 V, V+ = +4.75 V to +5.25 V, V
PP
= 210 V. REF_IN is buffered internally on the AD5535 and
should be driven from a stable reference source.
FUNCTIONAL BLOCK DIAGRAM
RF
R1
RF
R1
RF
R1
RF
R1
INTERFACE
CONTROL
LOGIC
DAC
DAC
DAC
DAC
DV
CC
AV
CC
SYNC
D
IN
SCLK
DGND
AGND
DAC_GND
RESET
REF_IN
V
PP
PGND
V
V
+
14-BIT BUS
ANODE
CATHODE
V
OUT
0
V
OUT
1
V
OUT
30
V
OUT
31
AD5535
05068-001
Figure 1.
background image
AD5535
Preliminary Technical Data
Rev. PrE | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Functional Description .................................................................. 11
Digital-to-Analog Section ......................................................... 11
Reset Function ............................................................................ 11
Serial Interface ............................................................................ 11
Microprocessor Interfacing....................................................... 11
Applications Information .............................................................. 13
MEMS Mirror Control Application......................................... 13
AD5535 Board Layout to Ensure Compliance with IPC-221
Specification................................................................................ 13
Power Supply Sequencing and Decoupling Recommendations
....................................................................................................... 14
Guidelines for Printed Circuit Board Layout ......................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
10/04--Revision PrE: Preliminary Version
background image
Preliminary Technical Data
AD5535
Rev. PrE | Page 3 of 16
SPECIFICATIONS
V
PP
= 210 V, V
-
= -5 V, V
+
= +5 V; AV
CC
= 5.25 V; DV
CC
= 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V;
all outputs unloaded. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
A Grade
2
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
Resolution
14
Bits
Integral Nonlinearity (INL)
0.1
% of FSR
Differential Nonlinearity (DNL)
0.5
1
LSB
Guaranteed monotonic
Zero Code Voltage
2 V
Offset Error
45
+45 mV
Offset Drift
0.09
LSB/C
Voltage Gain
47.5
50
52.5
V/V
Gain Temperature Coefficient
TBD
ppm/C
Channel-to-Channel Gain Match
5
%
Full-Scale Voltage Drift
8
ppm/C
OUTPUT CHARACTERISTICS
Output Voltage Range
3
0
V
PP
10
V
Output Impedance
50
Resistive Load
4, 5
1
M
Capacitive Load
4
200 pF
Short-Circuit Current
0.7
mA
DC Crosstalk
4
3 LSB
DC Power Supply Rejection (PSRR), V
PP
70
dB
AC CHARACTERISTICS
Settling Time
1/4 to 3/4 Scale Step
30
s No
load
100
s
200 pF load
1 LSB Step
10
s No
load
10
s
200 pF load
Slew Rate
10
V/s No
load
3
V/s
200 pF load
3 dB Bandwidth
5
kHz
Output Noise Spectral Density
TBD
nV/
Hz
Measured at 1 kHz
0.1 Hz to 10 Hz Output Noise Voltage
TBD
V p-p
Digital-to-Analog Glitch Impulse
TBD
nVs typ
1 LSB change around major carry
Digital Crosstalk
TBD
nVs typ
Analog Crosstalk
13
Vs typ
Digital Feedthrough
TBD
nVs typ
VOLTAGE REFERENCE, REF_IN
6
AV
CC
must exceed REFIN by 1.25 V min
Input Voltage Range
4
1
4.096 V
Input Current
1 A
TEMPERATURE MEASUREMENT DIODE
4
Peak Inverse Voltage, P
IV
5
V
Cathode to anode
Forward Diode Drop, V
F
0.8 V
I
F
= 2 mA, anode to cathode
Forward Diode Current, I
F
2
mA
Anode to cathode
V
F
Temperature Coefficient, T
C
1.44
mV/C
I
F
= 250 A
background image
AD5535
Preliminary Technical Data
Rev. PrE | Page 4 of 16
A Grade
2
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DIGITAL INPUTS
4
Input Current
5
10
A
Input Low Voltage
0.8 V
DV
CC
= 3 V to 5 V
Input High Voltage
2.0
V
DV
CC
= 3 V to 5 V
Input Hysteresis (SCLK and SYNC only)
200
mV
Input Capacitance
10 pF
POWER-SUPPLY VOLTAGES
V
PP
(50 REF_IN) +10
210
225
V
V
5.25
4.75
V
V
+
4.75
5.25
V
AV
CC
4.75
5.25
V
DV
CC
2.7
5.25
V
POWER-SUPPLY CURRENTS
7
I
PP
75
110
A/channel
I
-
2.5
3.5
mA
I
+
2.5
3.5
mA
AI
CC
16
20
mA
DI
CC
0.1
0.5
mA
POWER DISSIPATION
7
609
mW
1
See Terminology.
2
A Grade temperature range: -10C to +85C; typically +25C.
3
Linear output voltage range: +7 V to V
PP
- 10 V.
4
Guaranteed by design and characterization, not production tested.
5
Ensure that T
J
max is not exceeded. See the
section.
Absolute Maximum Ratings
6
Reference input determines output voltage range. Using a 4.096 V reference (REF 198) gives an output voltage range of 0 V to 200 V. Output range is programmable
via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to V
PP
- 10 V.
7
Outputs unloaded.
background image
Preliminary Technical Data
AD5535
Rev. PrE | Page 5 of 16
TIMING CHARACTERISTICS
V
PP
= 210 V, V
-
= 5 V, V
+
= +5 V; AV
CC
= 5.25 V; DV
CC
= 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V.
All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1,
2,
3
A Grade
Unit Conditions/Comments
f
UPDATE
1.2
MHz max
Channel Update Rate
f
CLKIN
30
MHz max
SCLK Frequency
t
1
13
ns min
SCLK High Pulse Width
t
2
13
ns min
SCLK Low Pulse Width
t
3
15 ns
min
SYNC Falling Edge to SCLK Falling Edge Setup Time
t
4
50 ns
min
SYNC Low Time
t
5
10 ns
min
SYNC High Time
t
6
10
ns min
DIN Setup Time
t
7
5
ns min
DIN Hold Time
t
8
200
ns min
19th SCLK Falling Edge to SYNC Falling Edge for Next Write
t
9
20 ns
min
RESET Pulse Width
1
See timing diagrams in Figure 2.
2
Guaranteed by design and characterization, not production tested.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
1
LSB
16
17
18
19
MSB
1
RESET
2
3
4
5
t
8
t
7
t
6
t
4
t
9
D
IN
SYNC
SCLK
t
5
t
3
t
2
t
1
05068-002
Figure 2. Serial Interface Timing Diagram

Document Outline