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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD53513
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
Quad Ultrahigh-Speed Pin Driver
with High-Z and V
TERM
Modes
FUNCTIONAL BLOCK DIAGRAM
20
ROUT
AD53513
GND
GND GND
GND
GND
TVCC
THERM
1.0 A/K
39nF
39nF
30
50
VCC1
VCC2
VCC3
VCC4
VEE1
VEE2
VEE3
VEE4
VCC
VEE
VH2
DATA2
DATAB2
INH2
INHB2
VL2
VT2
VBB
RLD2
RLD3
VBB
VH3
DATA3
DATAB3
INH3
INHB3
VL3
VT3
VH4
DATA4
DATAB4
INH4
INHB4
VL4
VT4
VBB
RLD4
RLD1
VBB
VH1
DATA1
DATAB1
INH1
INHB1
VL1
VT1
DRIVER 1
VHDCPL1
VOUT1
VLDCPL1
20
ROUT
39nF
39nF
30
50
VHDCPL2
VOUT2
VLDCPL2
DRIVER 2
20
ROUT
39nF
39nF
30
50
VHDCPL3
VOUT3
VLDCPL3
20
ROUT
39nF
39nF
30
50
VHDCPL4
VOUT4
VLDCPL4
DRIVER 4
DRIVER 3
FEATURES
500 MHz Driver Operation (1 Gb/s)
Driver Inhibit Function
100 ps Edge Matching
Guaranteed Industry Specifications
20
Output Impedance
5 V/ns Slew Rate
Variable Output Voltages for ECL, TTL, and CMOS
High-Speed Differential Inputs for Maximum Flexibility
Ultrasmall 100-Lead LQFP Package with Built-In
Heat Sink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTION
The AD53513 is a quad high-speed pin driver designed for use
in digital or mixed-signal test systems. Combining a high-speed
monolithic process with a convenient surface-mount package,
this product attains superb electrical performance while preserving
optimum packaging densities and long-term reliability in a
100-lead, LQFP package with built-in heat sink.
Featuring unity gain programmable output levels of 2.5 V to
+5.5 V, with output swing capability of less than 200 mV to
8 V, the AD53513 is designed to stimulate ECL, TTL, and
CMOS logic families, as well as high-speed memory. The
1.0 Gb/s data rate capacity and matched output impedance
allow for real-time stimulation of these digital logic families.
To test I/O devices, the pin driver can be switched into a high
impedance state (Inhibit Mode), electrically removing the driver
from the path. The pin driver leakage current in inhibit is typically
100 nA and output charge transfer entering inhibit is typically less
than 20 pC.
The AD53513 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high-speed differential inputs with a common-mode range of
2 V. This allows for direct interface to precision differential
ECL timing. The analog logic HI/LO inputs are equally easy
to interface. Typically requiring 10
A of bias current, the
AD53513 can be directly coupled to the output of a digital-
to-analog converter.
Each channel of the AD53513 has a Mode Select Pin RLD,
which is a single-sided logic input. The logic threshold is set by
the VBB input which is common to all four channels. The RLD
Mode Select controls whether inhibit puts the driver in High-Z
or V
TERM
mode. (Refer to Table I.) All of the digital logic inputs
(DATA, DATAB, INH, INHB, RLD, VBB), must share a
common set of logic levels. The VBB threshold should be set to
the midrange of the logic levels. For example, if ECL levels of
0.8 V to 1.8 V are used, VBB should be set to 1.3 V.
The AD53513 is available in a 100-lead, LQFP package with a
built-in heat sink and is specified to operate over the ambient
commercial temperature range of 25
C to +85C.
2
REV. 0
AD53513SPECIFICATIONS
(All specifications are at T
J
= 85 C 5 C, +V
S
= +9 V 3%, V
S
= 6 V 3% unless otherwise noted. All temperature coefficients are measured
at T
J
= 75 C95 C). (A 39 nF capacitor must be connected between V
CC
and V
HDCPL
and between V
EE
and V
LDCPL
.)
Parameter
Min
Typ
*
Max
Unit
Test Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
(Data to
DATA, INH to INH), RLD, VBB
V
BB
= 1.3 V
Input Voltage
2
0
Volts
Differential Input Range
ECL
Bias Current
1
+1
mA
V
IN
= 2 V, 0.0 V
VBB Threshold Input
Midrange
V
Set to Midrange of Logic Levels
REFERENCE INPUTS (V
L
, V
H
,
V
T
)
Bias Currents
50
+50
A
V
L
, V
H
= 2 V
OUTPUT CHARACTERISTICS
Logic High Range
2.3
+5.5
Volts
DATA = H
Logic Low Range
2.5
+5.3
Volts
DATA = L
Amplitude (V
H
V
L
)
0.2
8.0
Volts
Absolute Accuracy
V
H
Offset
100
+100
mV
DATA = H, V
H
= 0 V, V
L
= 2 V, V
T
= +3 V
V
H
Gain and Linearity Error
0.3 5
% of V
H
+ mV
DATA = H, V
H
= 2 V to +5 V, V
L
= 2.5 V,
V
T
= +3 V
V
L
Offset
100
+100
mV
DATA = L, V
L
= 0 V, V
H
= +5 V, V
T
= +4.5 V
V
L
Gain and Linearity Error
0.3 5
% of V
L
+ mV
DATA = L, V
L
= 2 V to +5 V, V
H
= +5.5 V,
V
T
= +4.5 V
V
T
Offset
100
+100
mV
Term Mode, V
T
= 0 V, V
L
= 1 V, V
H
= +3 V
V
T
Gain and Linearity Error
0.3 5
% of V
T
+ mV
Term Mode, V
T
= 2.0 V to +5.0 V, V
L
= 0,
V
H
= +3 V
Offset TC, V
H
, or V
L
, or V
TERM
0.5
mV/
C
V
L
, V
H
= 0 V
Output Resistance
20
DATA = H, V
H
= 3 V, V
L
= 0 V, I
OUT
= 45 mA
Output Leakage
1.0
+1.0
A
V
OUT
= 2 V to +5 V
Dynamic Current Limit
130
mA
C
BYP
= 39 nF, V
H
= +5 V, V
L
= 2 V
Static Current Limit
85
mA
Output to 2.5 V, V
H
= +5.5 V, V
L
= 2.5 V,
V
T
= 0; DATA = H and Output to 5.5 V,
V
H
= +5.5 V, V
L
= 2.5 V, V
T
= 0
V
L
= 3 V, DATA = L
PSRR, Drive Mode
35
dB
V
S
= V
S
3%
DYNAMIC PERFORMANCE, DRIVE
(V
H
and V
L
)
Propagation Delay Time
0.3
1.1
ns
Measured at 50%, V
H
= 800 mV, 50
Load,
V
L
= 800 mV
Propagation Delay TC
0.5
ps/
C
Measured at 50%, V
H
= 800 mV, 50
Load,
V
L
= 800 mV
Delay Matching, Edge to Edge
100
ps
Measured at 50%, V
H
= 800 mV, 50
Load,
V
L
= 800 mV
Rise and Fall Time
1 V Swing
300
ps
Measured 20%80%, V
L
= 0 V, V
H
= 1 V, V
T
= 2 V
2 V Swing
450
ps
Measured 10%90%, V
L
= 0 V, V
H
= 2 V, V
T
= 2 V
3 V Swing
650
ps
Measured 10%90%, V
L
= 0 V, V
H
= 3 V, V
T
= 2 V
Rise and Fall Time TC
1 V Swing
1
ps/
C
Measured 20%80%, V
L
= 0 V, V
H
= 1 V, V
T
= 2 V
2 V Swing
1
ps/
C
Measured 10%90%, V
L
= 0 V, V
H
= 2 V, V
T
= 2 V
3 V Swing
1
ps/
C
Measured 10%90%, V
L
= 0 V, V
H
= 3 V, V
T
= 2 V
Overshoot, Undershoot, and Preshoot
(6% +50 mV)
% of Step + mV
a. V
L
, V
H
= 0 V, +1 V, V
T
= 2 V, 50
b. V
L
, V
H
= 0 V, +3 V, V
T
= 2 V, 50
c. V
L
, V
H
= 0 V, +5 V, V
T
= 2 V, 50
Settling Time
to 15 mV
50
ns
V
L
= 0 V, V
H
= +0.5 V, V
T
= 2 V
to 4 mV
10
s
V
L
= 0 V, V
H
= +0.5 V, V
T
= 2 V
Delay Change vs. Pulsewidth
10
ps
V
L
= 0 V, V
H
= +2 V, V
T
= 2 V,
Pulsewidth/Period = 1.0 ns/4.0 ns, 30 ns/120 ns
Minimum Pulsewidth
2 V Swing
700
ps
700 ps Input, 10%/90% Output, V
T
= 2 V,
V
L
= 0 V, V
H
= +2 V, 50
Terminated
Toggle Rate
3.2
GHz
V
L
= 1.8 V, V
H
= 0.8 V, V
T
= 2 V,
V
OUT
> 300 mV p-p at 50
Terminated
3
REV. 0
AD53513
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53513 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1
Power Supply Voltage
+V
S
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V
V
S
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
+V
S
to V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Inputs
DATA,
DATA, INH, INH, RLD, VBB . . . . . . . +5 V, 3 V
DATA to
DATA, INH to INH, RLD, VBB . . . . . . . . .
3 V
V
H
, V
L
, V
T
to GND . . . . . . . . . . . . . . . . . . . . . . +7 V, 2 V
V
H
to V
L
(V
H
V
T
) and (V
T
V
L
) . . . . . . . . . . . . . . . .
9 V
Outputs
V
OUT
Short Circuit Duration . . . . . . . . . . . . . . . Indefinite
2
V
OUT
Range in Inhibit Mode
V
HDCPL
. . . . . Do Not Connect Except for Capacitor to V
CC
V
LDCPL
. . . . . Do Not Connect Except for Capacitor to V
EE
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 V, 0 V
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . . . 175
C
Storage Temperature . . . . . . . . . . . . . . . . 65
C to +150C
Lead Temperature (Soldering, 10 sec)
3
. . . . . . . . . . . 260
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Output
short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3
To ensure lead coplanarity (
0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24
C
5C (75F 10F) with relative humidity not to exceed 65%.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Shipment Method,
Package
Quantity Per
Package
Model
Description
Shipping Container
Option
AD53513JSQ
100-Lead LQFP-CDQUAD
Tray, 90 Pieces
SQ-100
Parameter
Min
Typ
*
Max
Unit
Test Conditions
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit
1.5
2.5
ns
Measured at 50%, V
H
= +2 V, V
L
= 2 V, V
T
= 2 V
Delay Time, Inhibit to Active
0.7
1.7
ns
Measured at 50%, V
H
= +2 V, V
L
= 2 V, V
T
= 2 V
I/O Spike
<200
mV p-p
V
H
= 0 V, V
L
= 0 V, V
T
= 2 V
Output Capacitance
6
pF
Driver Inhibited
DYNAMIC PERFORMANCE, V
TERM
Delay Time, Active to V
TERM
0.50
1.30
ns
Measured at 50%, V
H
= +0.8 V, V
L
= 0.8 V, V
T
= 0 V
Delay Time, V
TERM
to Active
0.45
1.25
ns
50
Terminated
Overshoot, Undershoot, and Preshoot
V
L
= 2 V, V
H
= +2 V, V
T
= 0 V
V
TERM
to V
L
or V
H
6%/75
mV
V
L
= 0.8 V, V
H
= +0.8 V, V
T
= 0 V
Output Terminated 50
POWER SUPPLIES
Total Supply Range
15
V
Positive Supply
9
V
Negative Supply
6
V
Positive Supply Current
570
mA
Negative Supply Current
570
mA
Total Power Dissipation
8.6
W
Temperature Sensor Gain Factor
1.0
A/K
R
LOAD
= 4.2 k
, V
SOURCE
= 9 V
NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
*Typical parameters are not production tested but guaranteed through characterization.
Specifications subject to change without notice.
4
C0154001/02(0)
PRINTED IN U.S.A.
AD53513
REV. 0
PIN CONFIGURATION
26
27
28
29
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
48
49
50
38
5
4
3
2
7
6
9
8
1
11
10
16
15
14
13
18
17
20
19
22
21
12
24
23
25
71
72
73
74
69
70
67
68
65
66
75
60
61
62
63
58
59
56
57
54
55
64
52
53
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD53513
HEAT SLUG
VT1
VT2
VHDCPL1
VCC
VCC
TVCC
THERM
PWRGND
VH1
PWRGND
PWRGND
VL1
PWRGND
VCC
VCC
PWRGND
VH2
PWRGND
PWRGND
VL2
PWRGND
VEE
VEE
RLD1
RLD2
NC
VBB
VT4
VT3
VHDCPL4
VCC
VCC
PWRGND
VH4
PWRGND
PWRGND
VL4
PWRGND
VCC
VCC
PWRGND
VH3
PWRGND
PWRGND
VL3
PWRGND
VEE
VEE
RLD4
RLD3
GND
DATA1
DATAB1
INH1
INB1
PWRGND
INHB2
INH2
VEE
VEE
DATAB2
DATA2
PWRGND
DATA3
DATAB3
VEE
VEE
INH3
INHB3
PWRGND
INHB4
INH4
DATAB4
DATA4
GND
HQGND1
HQGND1
OUT1
HQGND1
VLDCPL1
PWRGND
VHDCPL2
HQGND2
OUT2
HQGND2
HQGND2
VLDCPL2
PWRGND
VLDCPL3
HQGND3
HQGND3
OUT3
HQGND3
VHDCPL3
PWRGND
VLDCPL4
HQGND4
OUT4
HQGND4
HQGND4
NC = NO CONNECT
NOTE THAT THE DIE IS MOUNTED TO THE BACK OF THE HEAT SLUG.
THE PACKAGE IS MOUNTED TO THE BOARD HEAT SLUG UP.
s
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead LQFP_ED Package
(SQ-100)
TOP VIEW
(PINS DOWN)
1
25
26
49
76
100
75
50
0.551 (14.00) BSC
0.630 (16.00) BSC
0.472
(12.00)
BSC
0.472 (12.00) BSC
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
0.020 (0.50) BSC
LEAD PITCH
0.551
(14.00)
BSC
0.630
(16.00)
BSC
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
SEATING
PLANE
0.063 (1.60)
MAX
VIEW A
7
3.5
0
0.008 (0.20)
0.004 (0.09)
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
0.006 (0.15)
0.002 (0.05)
0.003 (0.08)
MAX
VIEW A
ROTATED 90 CCW
Table I. Driver Truth Table
Output
DATA
DATA
INH
INH
RLD
VBB
State
0
1
0
1
X
VBB
V
L
1
0
0
1
X
VBB
V
H
X
X
1
0
0
VBB
INH
X
X
1
0
1
VBB
V
TERM
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