EDD2508AETA-5C-E (Elpida) - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions, DDR SDRAM (256 Мб)

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EDD2508AETA-5C-E (Elpida)

Подробное описание (datasheet) электронного компонента «EDD2508AETA-5C-E» (DDR SDRAM (256 Мб)), производства Elpida. Выберите наиболее удобный формат.

Datasheet EDD2508AETA-5C-E производства Elpida

Маркировка	EDD2508AETA-5C-E
Описание	* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
Функционал	DDR SDRAM (256 Мб)
Производитель	Elpida Memory
Сайт	www.elpida.com

Размер	Страниц: 52, 584.15Кб
Скачать файл	Оригинальный PDF Архив WinZIP
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