EBE51AD8AGFA (Elpida) - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive, DDR2 SDRAM

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EBE51AD8AGFA (Elpida)

Подробное описание (datasheet) электронного компонента «EBE51AD8AGFA» (DDR2 SDRAM), производства Elpida. Выберите наиболее удобный формат.

Datasheet EBE51AD8AGFA производства Elpida

Маркировка	EBE51AD8AGFA
Описание	* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
Функционал	DDR2 SDRAM
Производитель	Elpida Memory
Сайт	www.elpida.com

Размер	Страниц: 23, 205.92Кб
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